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Patent # Description
US-7,064,373 Architecture and fabrication method of a vertical memory cell
A vertical memory cell comprises a storage capacitor, the inner electrode of which is formed in a deep trench, and a vertical selector transistor. The selection...
US-7,064,360 Bipolar transistor and method for fabricating it
A method is provided to fabricate a bipolar transistor with a low base connection resistance, low defect density and improved scalability. Scalability is to be...
US-7,064,176 Coating material for electronic components
The invention relates to novel polyhydroxyamide compounds that, in the form of their oxazoles, ane suited as a coating material, particularly for electronic...
US-7,063,921 Photomask, in particular alternating phase shift mask, with compensation structure
The invention relates to a method for the production of masks, in particular for the production of alternating phase shift masks (1), or of chromeless phase...
US-7,062,748 System and method of correcting mask rule violations after optical proximity correction
A method is provided for correcting rule violating areas of a photomask using a digital representation of the photomask. The method includes identifying...
US-7,062,701 Method for storing path metrics in a viterbi decoder
For a Virerbi decoder, it is proposed to combine the butterfly structures of the corresponding trellis diagram in pairs in such a way that for each butterfly...
US-7,062,690 System for testing fast synchronous digital circuits, particularly semiconductor memory chips
A system and a method for testing fast synchronous digital circuit with an additional built outside self test semiconductor chip disposed between a test device...
US-7,062,632 Method for controlling a central processing unit for addressing in relation to a memory and controller
The present invention is based on the finding that free CPU operation code identifiers of a CPU or CPU operation code identifiers useable for any reason can be...
US-7,062,606 Multi-threaded embedded processor using deterministic instruction memory to guarantee execution of pre-selected...
A multi-threaded embedded processor that includes an on-chip deterministic (e.g., scratch or locked cache) memory that persistently stores all instructions...
US-7,062,241 Signal processor and method for the system-independent digital evaluation of mobile communications reception...
Only a single, standard-independent clock rate is generated in a signal processor or a signal processing structure, and correspondingly only precisely one clock...
US-7,061,933 Multiplexer bus with local bus nodes
The invention relates to a multiplexer bus comprising local bus nodes. In order to connect a plurality of transmitting-receiving circuits, the latter are...
US-7,061,904 Integrated access device controller
A network processor (12) for a voice over Internet protocol phone integrates a universal serial bus port (56), a pair of IEEE 802.3 MACs (70a), a repeater (70b),...
US-7,061,797 Hybrid memory cell for spin-polarized electron current induced switching and writing/reading process using such...
A magnetoresistive hybrid memory cell includes first and second stacked structures. The first stacked structure includes a magnetic tunnel junction including...
US-7,061,787 Field ramp down for pinned synthetic antiferromagnet
Techniques for processing magnetic devices are provided. In one aspect, a method of processing a magnetic device including two or more anti-parallel coupled...
US-7,061,784 Semiconductor memory module
The invention relates to a semiconductor memory module having at least one memory chip and a buffer chip, which drives clock, address and command signals to the...
US-7,061,746 Semiconductor component with integrated capacitance structure having a plurality of metallization planes
A semiconductor component includes an insulating layer, which is configured on a semiconductor substrate and in which a capacitor structure is formed. The...
US-7,061,408 Concept for a secure data communication between electronic devices
An encoder for encoding a data word with a plurality of bits, wherein the data word is transmittable in parallel on a data bus, wherein one bit line is provided...
US-7,061,337 Amplitude control circuit
An amplitude control circuit comprises a first circuit configured to receive differential signals and provide a first signal based on the amplitudes of the...
US-7,061,305 Threshold voltage detector for process effect compensation
A process variation compensation circuit and method including a threshold voltage detector circuit, a comparator network, and a circuit block. The threshold...
US-7,061,296 Circuit arrangement for generating a digital clock signal
A circuit arrangement for generating a digital clock signal which manages without a crystal oscillator and has a low current consumption. The circuit arrangement...
US-7,061,272 Finite state machine circuit
A finite state machine (FSM) circuit including a random access memory (RAM) as the basic logical element and a multiplexer, which can be programmed to perform...
US-7,061,260 Calibration device for the calibration of a tester channel of a tester device and a test system
A calibration device for the calibration of a tester channel of a tester device is provided. The calibration device includes a connecting device and a planar...
US-7,061,227 Apparatus and method for calibrating a semiconductor test system
A process and device for calibrating a semiconductor component test system includes a first connection, at which a corresponding signal, in particular a...
US-7,061,098 Electronic component and method for its production
An electronic component includes a semiconductor die which exhibits on its active top side above an active surface area a self-supporting electrically conductive...
US-7,061,089 Memory module having space-saving arrangement of memory chips and memory chip therefore
A memory module has a module board having a main surface. A plurality of memory chips is arranged on the main surface of the module board. Each memory chip has...
US-7,061,046 Non-volatile semiconductor memory device
Bitline conductor tracks are arranged parallel to one another and electrically insulated from a substrate provided with a basic doping. A memory layer sequence,...
US-7,061,035 Self-aligned V0-contact for cell size reduction
An FeRAM comprising includes a ferroelectric material sandwiched between a top electrode and a bottom electrode. A V0-contact provides an electrical connection...
US-7,060,619 Reduction of the shear stress in copper via's in organic interlayer dielectric material
Interconnect layers on a semiconductor body containing logic circuits (microprocessors, Asics or others) or random access memory cells (DRAMS) are formed in a...
US-7,060,583 Method for manufacturing a bipolar transistor having a polysilicon emitter
In the inventive method for manufacturing a bipolar transistor having a polysilicon emitter, a collector region of a first conductivity type and, adjoining...
US-7,060,566 Standby current reduction over a process window with a trimmable well bias
An integrated circuit device including a plurality of MOSFETs of similar type and geometry is formed on a substrate with an ohmic contact, and an adjustable...
US-7,060,562 Method for fabricating gate electrodes in a field plate trench transistor, and field plate trench transistor
A method for fabricating gate electrodes (7) in a field plate trench transistor (1) having a cell array with a plurality of trenches (3) and a plurality of mesa...
US-7,060,558 Method for fabricating a field-effect transistor having a floating gate
In the course of a method for fabricating a field-effect transistor having a floating gate, a structure is formed which has uncovered sidewalls of a layer made...
US-7,060,534 Housing for semiconductor devices, semiconductor device pin, and method for the manufacturing of pins
A housing, in particular for semiconductor devices, a semiconductor device pin, and a method for the manufacturing of pins wherein at least one pin is punched...
US-7,060,529 Multiple chip semiconductor arrangement having electrical components in separating regions
A semiconductor packaging arrangement, or module, includes a printed circuit board having an electrical interconnect thereon and a semiconductor package mounted...
US-7,060,399 Reflective mirror for lithographic exposure and production method
A reflective optical mirror for semiconductor fabrication includes a capping layer above a reflective multilayer sequence. A doping is provided for the capping...
US-RE39,124 Integrated circuit having capacitive elements
An integrated circuit having capacitive elements for smoothing a supply voltage is described. In this case, at least one additional metal electrode, which is...
US-7,058,855 Emulation interface system
An integrated circuit with multiple circuit cores each of which have integrated emulated circuits, and an emulation interface module, such that the integrated...
US-7,058,851 Integrated memory and method of repairing an integrated memory
A method for repairing an integrated memory having first units of memory cells and second, redundant units of memory cells for replacing first units of memory...
US-7,058,840 Method and apparatus for generating a second signal having a clock based on a second clock from a first signal...
An apparatus for generating a second signal having a clock based on a second clock from a first signal with a first clock comprises first and second means for...
US-7,058,095 Tunable semiconductor laser and production method
A resonator structure containing an active layer is subdivided into at least two sections in which mode spacings differ from one another by 7 to 10 percent on...
US-7,057,961 Circuit and method for evaluating and controlling a refresh rate of memory cells of a dynamic memory
A circuit for controlling a refresh rate of memory cells of a dynamic memory includes a control circuit for controlling an access to memory cells of the dynamic...
US-7,057,924 Precharging the write path of an MRAM device for fast write operation
The write path of an MRAM device is precharged before starting a write operation of a magnetic memory cell, increasing the speed of the write operation and...
US-7,057,590 LED array implementation
An LED array arrangement that reduces the number of control inputs needed to operate it is described. The reduction in the number of control pins is achieved...
US-7,057,457 Low-noise amplifying circuit
A low-noise amplifier circuit is specified which has a switchable gain ratio. For this purpose, a parallel circuit comprising a first and a second current path...
US-7,057,454 Resistor and switch-minimized variable analog gain circuit
A DSM variable high-gain circuit includes a differential amplifier and a negative feedback loop comprising low resistance poly resistors and switches configured...
US-7,057,422 Comparator
An arrangement and a method in an integrated circuit for tuning and setting a value comprising a comparator circuit having a reference voltage input and a...
US-7,057,271 Apparatus for connecting an IC terminal to a reference potential
A circuit chip has an apparatus for an electrically conductive connection of a terminal thereof to an external reference potential. The apparatus has a parallel...
US-7,057,253 Combination of intrinsic and shape anisotropy for reduced switching field fluctuations
A magnetic memory cell and method of manufacturing thereof, wherein the angle between the shape anisotropy axis and the intrinsic anisotropy axis of the magnetic...
US-7,057,232 Semiconductor structure with integrated shield
A semiconductor structure comprises a memory element, which comprises a floating gate, a control electrode, which is capacitively coupled to the floating gate,...
US-7,057,224 Semiconductor memory having an arrangement of memory cells
A semiconductor memory can have first lines to which memory cells are connected and that run divergently with respect to one another, and second lines to which...
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