Easy To Use Patents Search & Patent Lawyer Directory

At Patents you can conduct a Patent Search, File a Patent Application, find a Patent Attorney, or search available technology through our Patent Exchange. Patents are available using simple keyword or date criteria. If you are looking to hire a patent attorney, you've come to the right place. Protect your idea and hire a patent lawyer.

Searching: infineon





Search by keyword, patent number, inventor, assignee, city or state:




Patent # Description
US-7,047,334 Device for supplying control signals to memory units, and a memory unit adapted thereto
A device for supplying control signals to memory units of a memory module comprises a first bus section for supplying a first part of the control signals to a...
US-7,047,155 Bus interface
A bus interface connects a device to a bus that connects a plurality of devices to one another. The bus interface described is distinguished in that a timer...
US-7,046,797 Telephone system with controllable ringing voltage
A telephone system includes a controllable ringing generator for generating a ringing signal and an interface for providing a ringing voltage derived from that...
US-7,046,564 Semiconductor memory
The invention relates to semiconductor memories, and in particular, to DRAMs with a memory subunit including a memory cell in which a data value is stored and...
US-7,046,363 Optical measurement system and method
An apparatus and method for measuring feature sizes having form birefringence. The method includes providing a surface having surface features thereon; radiating...
US-7,046,178 Method and device for the calibration of a weighted network
Improved methods for the calibration, in particular for self-calibration, of an A/D or D/A converter with weighted network (CN) are proposed. Only a relevant...
US-7,046,081 Amplifier circuit with passive gain step circuit
An amplifier circuit includes an amplifier connected between an HF input and HF output and a coupling circuit connected in parallel to the amplifier between the...
US-7,046,060 Method and apparatus compensating for frequency drift in a delay locked loop
A delay locked loop (DLL) according to the present invention includes a cycle time detector to determine the quantity of delay elements within a clock cycle and...
US-7,045,881 Electronic component with shielding and method for its production
An electronic component with shielding is described. The component has a semiconductor chip with a semiconductor substrate. Disposed in a region of a rear side...
US-7,045,855 Semiconductor device and corresponding fabrication method
A semiconductor device having a gate structure, the gate structure having a first gate dielectric made of a first material having a first thickness and a first...
US-7,045,837 Hardmask with high selectivity for Ir barriers for ferroelectric capacitor manufacturing
The present invention provides a ferroelectric device relatively free of fences by using a hardmask having high etching selectivity relative to an underlying...
US-7,045,422 Semiconductor gate structure and method for fabricating a semiconductor gate structure
A method for fabricating a semiconductor gate structure including depositing at least one sacrificial layer on a semiconductor substrate; patterning the at least...
US-7,045,274 Process for structuring a photoresist by UV at less than 160 NM and then aromatic and/or alicyclic amplification
A process amplifies structured resists by utilizing a reaction between a nucleophilic group and an isocyanate group or thiocyanate group to link an amplification...
US-7,045,273 Process for silylating photoresists in the UV range
A process for the amplification of structured resists utilizes a reaction between a nucleophilic group and an isocyanate group or thiocyanate group to link an...
US-7,045,254 Mask with programmed defects and method for the fabrication thereof
A mask, and in particular a phase shift product mask, utilizes predetermined defects being produced during the fabrication thereof in the so-called "second...
US-7,045,070 Method of producing an electrode configuration and method of electrically contacting the electrode configuration
The electrode configuration includes at least one structured layer. A mask is produced on the layer to be structured and the layer is dry etched. The mask is at...
US-7,043,653 Method and apparatus for synchronous signal transmission between at least two logic or memory components
An internal clock signal of a logic/memory component that receives signals is transmitted as a reference clock to a transmitting logic/memory component. With the...
US-7,043,625 Method and apparatus for adding user-defined execution units to a processor using configurable long instruction...
The present invention is a system in which a multiplicity of diverse dedicated hardware off-core execution units are connected to a core processor in order to...
US-7,043,197 Telecommunication system for the bidirectional transmission of data and voice signals
Telecommunication system for bidirectional transmission of data and voice signals with a data network (2), which is connected via a satellite data transmission...
US-7,042,953 Method and arrangement for compensating signal echoes during duplex data transmission with discrete multitone...
A system and method for compensating for signal echoes during duplex data transmission with discrete multitone modulation includes determining, the error of a...
US-7,042,789 Energy storing memory circuit
The invention relates to a memory arrangement having an energy storage device (store) which collects the energy transported during the flowing of a write or read...
US-7,042,786 Memory with adjustable access time
A memory comprising a memory array, an address buffer configured to receive an external address, a refresh address counter configured to generate a refresh...
US-7,042,785 Method and apparatus for controlling refresh cycles of a plural cycle refresh scheme in a dynamic memory
According to the present invention, refresh operation of a device employing a plural refresh cycle scheme is controlled. The refresh scheme employed by the...
US-7,042,777 Memory device with non-variable write latency
One embodiment of the present invention provides a random access memory including a command block and an array of memory cells. The command block is configured...
US-7,042,773 Integrated circuit for storing operating parameters
An integrated circuit includes a programming circuit (10) for generating programming signals (PS1, . . . , PS4) with a first input terminal (E1) for applying a...
US-7,042,705 Sidewall structure and method of fabrication for reducing oxygen diffusion to contact plugs during CW hole...
The present invention provides a sidewall oxygen diffusion barrier and a method for fabricating the sidewall oxygen diffusion barrier that reduces the diffusion...
US-7,042,281 Circuit arrangement for voltage regulation
Circuit arrangement for voltage regulation having a differential amplifier having first and second inputs and first and second outputs, wherein a reference...
US-7,042,249 Method for actuating a transistor
The present invention provides a method for actuating a transistor (10) having the following steps: (a) a first predetermined positive potential is applied to a...
US-7,042,206 Integrated circuit and method for operating the integrated circuit
An integrated circuit has connecting pads for outputting digital signals, a connection for a time reference signal, and an assessment circuit to measure and...
US-7,042,094 Via structure for semiconductor chip
A multi-level via structure for a semiconductor chip in which the collective area of a vias structure is not entirely oriented directly in-line with the...
US-7,042,037 Semiconductor device
Disclosed is a semiconductor device comprising a semiconductor substrate, a capacitor provided above the semiconductor substrate and including a bottom...
US-7,041,574 Composite intermetal dielectric structure including low-k dielectric material
A method of forming a composite intermetal dielectric structure is provided. An initial intermetal dielectric structure is provided, which includes a first...
US-7,041,568 Method for the production of a self-adjusted structure on a semiconductor wafer
A structure on a layer surface of the semiconductor wafer has at least one first area region (8, 9), which is reflective for electromagnetic radiation, and at...
US-7,041,551 Device and a method for forming a capacitor device
A device and method for forming a capacitor device comprises forming a substrate, forming a first interlayer dielectric layer on the substrate and forming two or...
US-7,041,545 Method for producing semiconductor memory devices and integrated memory device
The invention provides an integration scheme for a memory cell array, especially a charge-trapping memory cell array, comprising an architecture of local...
US-7,041,426 Photoresist based on polycondensates and having an increased resolution for use in 157 nanometer lithography
A photoresist includes a polymer which has acid-cleavable groups in its main chain. The polymer can thus be cleaved by acid into short cleavage products which...
US-7,040,173 Pressure sensor and method for operating a pressure sensor
A pressure sensor having a substrate, a counter-structure applied to the substrate, a dielectric on the counter-structure, a membrane on the dielectric, wherein...
US-7,039,915 Method and apparatus for software-based allocation and scheduling of hardware resources in an electronic device
An architecture and method for dynamic resource allocation and scheduling in a communication device is disclosed herein. The method of controlling hardware...
US-7,039,907 Method of protecting entry addresses
An efficient method for protecting entry addresses in computer programs allows direct jumps to permissible entry addresses. The permissible entry addresses are...
US-7,039,838 Method for testing a circuit unit to be tested and test apparatus
The invention provides a method for testing a circuit unit (101) to be tested, in which a test time is reduced, at least one word line (102a 102N) of the circuit...
US-7,039,544 Method for testing circuit units to be tested and test apparatus
The invention provides a test apparatus for testing circuit units (101a 101k) to be tested by means of a test system (100), having a connection device (102),...
US-7,039,143 Circuit for determining the time difference between edges of a first digital signal and of a second digital signal
The circuit has a first input for supplying a first signal (S1) to a series circuit made from a plurality of basic elements. Each basic element has a memory (M)...
US-7,039,090 Method for controlling antennas of a receiving device in a radio system
A method for controlling antennas of a receiving device in a radio system, especially in a mobile radio system, in which at least one change is made using a...
US-7,038,956 Apparatus and method for reading out defect information items from an integrated chip
One embodiment of the invention provides a method for providing defect information from an integrated memory chip having dynamic memory cells arranged on word...
US-7,038,523 Voltage trimming circuit
Methods and circuits for minimizing or eliminating the effect of trimming circuits in a voltage generating circuit are provided. In general, the effects of...
US-7,038,447 Sensor circuit and method of producing it
A sensor circuit includes a sensor element, a current source for supplying an operating current for the sensor element and an amplifier circuit for amplifying a...
US-7,038,307 Semiconductor chip with FIB protection
The present disclosure is directed to a semiconductor chip having protection against focused ion beam (FIB) attack. The semiconductor chip includes a conductor...
US-7,038,272 Method for forming a channel zone of a transistor and NMOS transistor
In a method for forming a channel zone in field-effect transistors, a polysilicon layer is patterned above the channel zone to be formed. The polysilicon layer...
US-7,038,255 Integrated circuit arrangement having PNP and NPN bipolar transistors, and fabrication method
An explanation is given of, inter alia, an integrated circuit arrangement (100) containing an npn transistor (102) and a pnp transistor (104). Transistors with...
US-7,037,844 Method for manufacturing a housing for a chip having a micromechanical structure
A method for manufacturing a chip housing includes a first basis having a photolithograpically structurable layer on a main face, structured into a cover. A chip...
← Previous | 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 | Next →

File A Patent Application

  • Protect your idea -- Don't let someone else file first. Learn more.

  • 3 Easy Steps -- Complete Form, application Review, and File. See our process.

  • Attorney Review -- Have your application reviewed by a Patent Attorney. See what's included.