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Process for structuring a photoresist by UV at less than 160 NM and then
aromatic and/or alicyclic amplification
A process amplifies structured resists by utilizing a reaction between a nucleophilic group and an isocyanate group or thiocyanate group to link an amplification...
Process for silylating photoresists in the UV range
A process for the amplification of structured resists utilizes a reaction between a nucleophilic group and an isocyanate group or thiocyanate group to link an...
Mask with programmed defects and method for the fabrication thereof
A mask, and in particular a phase shift product mask, utilizes predetermined defects being produced during the fabrication thereof in the so-called "second...
Method of producing an electrode configuration and method of electrically
contacting the electrode configuration
The electrode configuration includes at least one structured layer. A mask is produced on the layer to be structured and the layer is dry etched. The mask is at...
Method and apparatus for synchronous signal transmission between at least
two logic or memory components
An internal clock signal of a logic/memory component that receives signals is transmitted as a reference clock to a transmitting logic/memory component. With the...
Method and apparatus for adding user-defined execution units to a
processor using configurable long instruction...
The present invention is a system in which a multiplicity of diverse dedicated hardware off-core execution units are connected to a core processor in order to...
Telecommunication system for the bidirectional transmission of data and
Telecommunication system for bidirectional transmission of data and voice signals with a data network (2), which is connected via a satellite data transmission...
Method and arrangement for compensating signal echoes during duplex data
transmission with discrete multitone...
A system and method for compensating for signal echoes during duplex data transmission with discrete multitone modulation includes determining, the error of a...
Energy storing memory circuit
The invention relates to a memory arrangement having an energy storage device (store) which collects the energy transported during the flowing of a write or read...
Memory with adjustable access time
A memory comprising a memory array, an address buffer configured to receive an external address, a refresh address counter configured to generate a refresh...
Method and apparatus for controlling refresh cycles of a plural cycle
refresh scheme in a dynamic memory
According to the present invention, refresh operation of a device employing a plural refresh cycle scheme is controlled. The refresh scheme employed by the...
Memory device with non-variable write latency
One embodiment of the present invention provides a random access memory including a command block and an array of memory cells. The command block is configured...
Integrated circuit for storing operating parameters
An integrated circuit includes a programming circuit (10) for generating programming signals (PS1, . . . , PS4) with a first input terminal (E1) for applying a...
Sidewall structure and method of fabrication for reducing oxygen diffusion
to contact plugs during CW hole...
The present invention provides a sidewall oxygen diffusion barrier and a method for fabricating the sidewall oxygen diffusion barrier that reduces the diffusion...
Circuit arrangement for voltage regulation
Circuit arrangement for voltage regulation having a differential amplifier having first and second inputs and first and second outputs, wherein a reference...
Method for actuating a transistor
The present invention provides a method for actuating a transistor (10) having the following steps: (a) a first predetermined positive potential is applied to a...
Integrated circuit and method for operating the integrated circuit
An integrated circuit has connecting pads for outputting digital signals, a connection for a time reference signal, and an assessment circuit to measure and...
Via structure for semiconductor chip
A multi-level via structure for a semiconductor chip in which the collective area of a vias structure is not entirely oriented directly in-line with the...
Disclosed is a semiconductor device comprising a semiconductor substrate, a capacitor provided above the semiconductor substrate and including a bottom...
Composite intermetal dielectric structure including low-k dielectric
A method of forming a composite intermetal dielectric structure is provided. An initial intermetal dielectric structure is provided, which includes a first...
Method for the production of a self-adjusted structure on a semiconductor
A structure on a layer surface of the semiconductor wafer has at least one first area region (8, 9), which is reflective for electromagnetic radiation, and at...
Device and a method for forming a capacitor device
A device and method for forming a capacitor device comprises forming a substrate, forming a first interlayer dielectric layer on the substrate and forming two or...
Method for producing semiconductor memory devices and integrated memory
The invention provides an integration scheme for a memory cell array, especially a charge-trapping memory cell array, comprising an architecture of local...
Photoresist based on polycondensates and having an increased resolution
for use in 157 nanometer lithography
A photoresist includes a polymer which has acid-cleavable groups in its main chain. The polymer can thus be cleaved by acid into short cleavage products which...
Pressure sensor and method for operating a pressure sensor
A pressure sensor having a substrate, a counter-structure applied to the substrate, a dielectric on the counter-structure, a membrane on the dielectric, wherein...
Method and apparatus for software-based allocation and scheduling of
hardware resources in an electronic device
An architecture and method for dynamic resource allocation and scheduling in a communication device is disclosed herein. The method of controlling hardware...
Method of protecting entry addresses
An efficient method for protecting entry addresses in computer programs allows direct jumps to permissible entry addresses. The permissible entry addresses are...
Method for testing a circuit unit to be tested and test apparatus
The invention provides a method for testing a circuit unit (101) to be tested, in which a test time is reduced, at least one word line (102a 102N) of the circuit...
Method for testing circuit units to be tested and test apparatus
The invention provides a test apparatus for testing circuit units (101a 101k) to be tested by means of a test system (100), having a connection device (102),...
Circuit for determining the time difference between edges of a first
digital signal and of a second digital signal
The circuit has a first input for supplying a first signal (S1) to a series circuit made from a plurality of basic elements. Each basic element has a memory (M)...
Method for controlling antennas of a receiving device in a radio system
A method for controlling antennas of a receiving device in a radio system, especially in a mobile radio system, in which at least one change is made using a...
Apparatus and method for reading out defect information items from an
One embodiment of the invention provides a method for providing defect information from an integrated memory chip having dynamic memory cells arranged on word...
Voltage trimming circuit
Methods and circuits for minimizing or eliminating the effect of trimming circuits in a voltage generating circuit are provided. In general, the effects of...
Sensor circuit and method of producing it
A sensor circuit includes a sensor element, a current source for supplying an operating current for the sensor element and an amplifier circuit for amplifying a...
Semiconductor chip with FIB protection
The present disclosure is directed to a semiconductor chip having protection against focused ion beam (FIB) attack. The semiconductor chip includes a conductor...
Method for forming a channel zone of a transistor and NMOS transistor
In a method for forming a channel zone in field-effect transistors, a polysilicon layer is patterned above the channel zone to be formed. The polysilicon layer...
Integrated circuit arrangement having PNP and NPN bipolar transistors, and
An explanation is given of, inter alia, an integrated circuit arrangement (100) containing an npn transistor (102) and a pnp transistor (104). Transistors with...
Method for manufacturing a housing for a chip having a micromechanical
A method for manufacturing a chip housing includes a first basis having a photolithograpically structurable layer on a main face, structured into a cover. A chip...
Process for producing an etching mask on a microstructure, in particular a
semiconductor structure with trench...
Process for producing an etching mask on a microstructure, in particular a semiconductor structure with trench capacitors, and corresponding uses of the etching...
Method of producing an electronic component
An electronic component includes a semiconductor chip that has an active upper side with integrated circuits and a passive rear side. The rear side and the side...
Method and apparatus for connecting at least one chip to an external
An electrically conductive connection is produced between a chip and an external wiring configuration that is kept at a distance from the chip by spacers....
Integrated security circuit
An integrated security circuit, for example, a microcontroller for smart cards, includes a function unit executing a security function. A control device...
Microprocessor configuration with encryption
A microprocessor configuration includes a data bus for data transfer between functional units. On the bus side, each unit contains an encryption/decryption unit...
Method and apparatus for placing an integrated circuit into a default mode
An integrated circuit having a signal bus carrying address signals includes mode selection means. The mode selection means has a default state and a non-default...
WLAN error control
A method in a wireless communications network is disclosed whereby errors due to incorrect transmission of scrambler seed values can be very greatly reduced....
A circuit comprises a first supply line and a second supply line. A capacitor is arranged between the first supply line and the second supply line. The first...
Memory device with column select being variably delayed
A memory device (10) includes an array (12) of memory cells arranged in rows and columns. Preferably, each memory cell includes a pass transistor coupled to a...
Memory system and memory subsystem
A memory system has a circuit board provided with a first slot connector into which a first memory module is inserted. A second slot connector is provided into...
Microscope arrangement for inspecting a substrate
A microscope measuring arrangement for inspecting a substrate includes a microscope, an illuminating system, preferably a sight glass, a holder, a substrate...
Signal processing unit and method for a digital TV system with an
increased frame rate video signal
A signal processing unit for a digital TV system comprises a first device which acts on a video signal with graphical picture elements and text characters. A...