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Patent # Description
US-7,054,714 Installation for processing a semiconductor wafer and method for operating the installation
An installation for processing a semiconductor wafer includes a semiconductor fabrication device having a load port, on which an identity code that can be read...
US-7,054,469 Passivation layer structure
A conductor layer is patterned into flat portions, for example of a fingerprint sensor that effects capacitive measurement. The conductor layer is fragmented in...
US-7,054,376 High data rate ethernet transport facility over digital subscriber lines
A facility transport system for transporting high speed Ethernet data over digital subscriber lines. The system, referred to as 100BaseS, is capable of...
US-7,054,206 Sub-column-repair-circuit
An arrangement for repairing at least one faulty bit line of a memory includes three multiplexer stages. The memory has a plurality of columns, each column...
US-7,054,180 Method and circuit for adjusting a resistance in an integrated circuit
A method for adjusting a resistance in an integrated circuit, the resistance having a first conductive area and a second conductive area between which a...
US-7,054,124 Method for switching over a reference voltage potential for overvoltage protection devices
Method for supplying a circuit unit (201) which is to be supplied with different supply voltages, in which the circuit unit (201) to be supplied is protected...
US-7,054,123 Circuit configuration for identifying a fault state
To identify a fault state, for example, a break in a supply line, while maintaining operational reliability, a circuit configuration for identifying a fault...
US-7,053,801 High rate coding for media noise
An apparatus has a conversion circuit, a precoder circuit, and a selection circuit. The conversion circuit converts user data b.sub.1, b.sub.2, b.sub.3 . . ....
US-7,053,722 Voltage controlled oscillator (VCO) with output buffer
An oscillator system is disclosed and includes an oscillator circuit having a differential output producing a differential output signal thereat having a...
US-7,053,711 Multistage differential amplifier
The invention relates to a multistage differential amplifier circuit having a multistage differential amplifier which has an input stage and at least one output...
US-7,053,682 Device and method for clock generation
A clock generator includes an interface for receiving a plurality of n periodical signals of the same frequency which are phase-shifted with respect to each...
US-7,053,681 Comparator and method for amplifying an input signal
The invention is aimed at providing a novel semi-conductor component, as well as a novel process for reading test data. There is a process for reading test data...
US-7,053,676 Circuit arrangement for generating a signal having a specific waveform with an adjustable voltage level
A circuit arrangement for generating specific waveforms includes a controllable voltage transformer circuit for generating an output signal (V.sub.OUT) with a...
US-7,053,655 Multi-level driver stage
An inventive driver stage for driving an output on one of n-levels, which are each spaced from each other by a voltage difference of .DELTA.V, includes a...
US-7,053,592 Output level responsive switching on/off of a linear regulator
A circuit configuration provides an output voltage from an input voltage. The circuit configuration has a voltage regulator with an input terminal for receiving...
US-7,053,474 Semiconductor component having at least two chips which are integrated in a housing and with which contact is...
A semiconductor component, featuring a housing, at least two semiconductor chips arranged in the housing, which chips in each case have a front side and a rear...
US-7,053,454 Semiconductor component, method for producing the semiconductor component, and method for producing electrical...
A fabrication method produces an integrated component on a semiconductor substrate and having a plurality of electrode connections formed to project from to the...
US-7,053,447 Charge-trapping semiconductor memory device
Memory cells are formed by preferably cylindrical recesses at the main surface of a semiconductor substrate, containing a memory layer sequence at sidewalls and...
US-7,053,428 Digital magnetic memory cell device
A digital magnetic memory cell device for read and/or write operations includes a soft-magnetic read and/or write layer system and at least one hard-magnetic...
US-7,052,990 Sealed pores in low-k material damascene conductive structures
An oxide layer is used to seal pores in porous low-dielectric constant materials, thus preventing the migration of subsequently deposited copper materials into...
US-7,052,970 Method for producing insulator structures including a main layer and a barrier layer
In order to produce insulator structures (8), insulator trenches (21) with aspect ratios of greater than 4:1 are introduced into a semiconductor substrate (1)...
US-7,052,936 Use of polybenzoxazoles (PBOS) for adhesion
The present invention describes the use of polybenzoxazoles (PBOs) for adhesively bonding articles or materials, especially components used in the semiconductor...
US-7,052,820 Silicon-containing resist for photolithography
A photoresist includes a polymer having a main chain composed of alternating silicon and oxygen atoms and a polymer chain segment which linked as a side chain to...
US-7,052,808 Transmission mask with differential attenuation to improve ISO-dense proximity
An apparatus, system and method to compensate for the proximity effects in the imaging of patterns in a photolithography process. A light exposure of a...
US-7,052,621 Bilayered metal hardmasks for use in Dual Damascene etch schemes
A metal hardmask for use with a Dual Damascene process used in the manufacturing of semiconductor devices. The metal hardmask has advantageous translucent...
US-7,051,253 Pseudo fail bit map generation for RAMS during component test and burn-in in a manufacturing environment
According to an embodiment of the present invention, a method is provided for determining a fail string for a device. The method includes determining a test...
US-7,051,237 Program-controlled unit
A program-controlled unit has debug resources that outputs trace information including selected addresses, data and/or control signals and that can be used to...
US-7,050,826 Hardware structure for a transmission/reception device for mobile radio applications, and method for processing...
A transmission/reception device for mobile radio applications has a microprocessor (DSP), at least one task-specific processor (P1, P2, P3) and a processor...
US-7,050,763 Method and device for transferring a signal from a signal source to a signal sink in a system
The system has at least two electronic units between which signals are transferred from a first electronic unit and a second electronic unit. The first...
US-7,050,584 Method and system for regenerating a private key for a predetermined asymmetric cryptographic key pair
After a key pair with a public key and a corresponding private key has been determined on the basis of an initial value, the initial value is made available to a...
US-7,050,487 Method and circuit arrangement for determination of transmission parameters
The invention relates to a method and an apparatus for determination of parameters for a transmission path in a telecommunications system by a ...
US-7,050,340 Semiconductor memory system and method for the transfer of write and read data signals in a semiconductor...
A semiconductor memory system for the transfer of write and read data signals among interface circuits includes at least one memory device, a memory controller...
US-7,050,073 Method and apparatus for scrolling an image to be presented on a display unit
In order to enable the gentlest possible scrolling of an image to be presented on a display unit, without restricting the scrolling range and with a low outlay,...
US-7,049,930 Arrangement of several resistors jointly positioned in a well of a semiconductor device, and a semiconductor...
An arrangement of several resistors jointly positioned in one and the same well of a semiconductor device, as well as to a semiconductor device including at...
US-7,049,884 Demodulation arrangement for a radio signal
A demodulation arrangement for a radio signal is disclosed wherein an I/Q mixer converts the radio signal to a real and an imaginary component and supplies the...
US-7,049,877 Switched level-shift circuit
Switched level-shift circuit (SLSC) for a signal-switch (1) which is provided for switching an applied analog input signal (V.sub.AIN), wherein the switched...
US-7,049,871 D-type flip-flop with a reduced number of transistors
A flip-flop includes a clock signal input, a data signal input, non-inverting and inverting outputs, a data acceptance unit, and a storage unit having a feedback...
US-7,049,854 sense amplifier having low-voltage threshold transistors
The invention provides a sense amplifier apparatus (100) for bit line signals (103, 104) having a bit line pair which comprises two bit lines (107, 108) to which...
US-7,049,832 Circuit arrangement and method for determining the load current through an inductive load connected to a supply...
Circuit arrangement for determining the load current through an inductive load (L) connected to a supply voltage (Vbat) in a clocked manner includes a current...
US-7,049,669 LDMOS transistor
A semiconductor device comprises an active region of a first conductivity type including a transistor structure, and a ring shaped region of the first...
US-7,049,656 Field-effect-controllable semiconductor configuration with a laterally extending channel zone
A semiconductor configuration includes a semiconductor body with a first connection zone of a first conductivity type, a second connection zone of the first...
US-7,049,651 Charge-trapping memory device including high permittivity strips
The charge-trapping layer comprises two strips above the source and drain junctions. The thicknesses of the charge-trapping layer and the gate dielectric are...
US-7,049,647 Semiconductor memory cell with trench capacitor and selection transistor and method for fabricating it
A semiconductor memory cell is formed in a substrate and includes a trench capacitor and a selection transistor. The trench capacitor includes a capacitor...
US-7,049,628 Semiconductor memory cell and semiconductor memory device
The semiconductor memory cell is characterized in that at least one modulation region is provided between a first gate electrode of the gate electrode...
US-7,049,241 Method for forming a trench in a layer or a layer stack on a semiconductor wafer
Preferably using a positive resist, a resist ridge (20) is formed in a photosensitive resist (16) applied on a semiconductor wafer (1) above a hard mask layer...
US-7,049,228 Method for introducing structures which have different dimensions into a substrate
A process for introducing structures that have different dimensions, particularly with regard to depth, in which just one lithography level is required, is...
US-7,049,193 Maskless middle-of-line liner deposition
A process for fabricating a semiconductor structure, wherein the semiconductor structure includes a core region and a periphery region. The core region includes...
US-7,048,450 Optoelectronic module with transmitter chip and connecting piece for the module with respect to an optical...
An optoelectronic module and a connecting piece for the module with respect to an optical fiber and with respect to a circuit board can have a semiconductor chip...
US-7,047,454 Integrated circuit having a data processing unit and a buffer memory
An integrated circuit includes a data processing unit, a buffer memory, and a setting memory. The buffer memory performs the function of registers for storing...
US-7,047,371 Integrated memory having a memory cell array containing a plurality of memory banks, and circuit configuration...
An integrated memory has at least two connection panels, which can be operated independently of one another, for external communication by the memory. In...
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