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Patent # Description
US-7,092,304 Semiconductor memory
A dummy capacitor drive potential VDC is given to one electrode of a dummy capacitor, and a reference potential for determining a data value of a memory cell is...
US-7,092,303 Dynamic memory and method for testing a dynamic memory
The invention relates to a dynamic memory having a memory cell array, a test controller to test the memory cell array and an oscillator to control the refreshing...
US-7,092,300 Memory apparatus having a short word line cycle time and method for operating a memory apparatus
Memory apparatus having a short word line cycle time and method for operating a memory apparatus. One embodiment provides a memory apparatus comprising at least...
US-7,092,284 MRAM with magnetic via for storage of information and field sensor
A magnetic memory element is disclosed. The magnetic memory element includes a magnetic via for storing information, made of a magnetic material and being...
US-7,092,274 Ferroelectric memory device
A ferroelectric memory device includes a memory cell array having memory cells arranged in a matrix form. Each of the memory cells includes a cell transistor and...
US-7,092,266 Circuit arrangement for supplying voltage to a load
A circuit arrangement supplies voltage to a load during normal operation and in a standby mode. The arrangement has the following features: input terminals for...
US-7,091,770 Circuit arrangement for voltage regulation
Circuit arrangement for voltage regulation having a voltage divider and a regulating circuit. The voltage divider is arranged between a first potential and a...
US-7,091,764 Duty distortion detector
A duty distortion detector comprises a first synchronous mirror delay configured to mirror a first signal with respect to a clock signal to provide a second...
US-7,091,612 Dual damascene structure and method
A dual damascene structure and method of fabrication thereof. An insulating layer comprises a first dielectric material and a second dielectric material, the...
US-7,091,595 Semiconductor device with semiconductor chip and rewiring layer and method for producing the same
The invention relates to a semiconductor device with a semiconductor chip and a rewiring layer, the semiconductor chip being embedded in a housing plastics...
US-7,091,573 Power transistor
The power transistor has a trench cell in a semiconductor body. A lower edge of the gate electrode has a profile which is not horizontal, i.e., not planar with...
US-7,091,557 Semiconductor component with increased dielectric strength and/or reduced on resistance
The invention relates to a semiconductor component having a first semiconductor zone of a first conduction type, a second semiconductor zone of a second...
US-7,091,553 Top oxide nitride liner integration scheme for vertical DRAM
A process and intermediate DRAM structure formed by providing a substrate having an array of trenches containing trench capacitors underlying vertical...
US-7,091,547 Semiconductor storage location
A semiconductor memory cell, in particular, in a DRAM memory cell array, includes a selection transistor and a storage capacitor. The storage capacitor has a...
US-7,091,533 Semiconductor component
The invention relates to a semiconductor component, in which regions of the conduction type opposite to the conduction type of the drift zone are incorporated in...
US-7,091,115 Method for doping a semiconductor body
The invention relates to a method for doping a semiconductor body (2), in which an n-type doping is introduced into the semiconductor body, which is initially...
US-7,091,103 TEOS assisted oxide CMP process
CMP of integrated circuits containing DRAM arrays with trench capacitors fill the trenches with oxide, resulting in a an array of oxide structures that is dense...
US-7,091,100 Polysilicon bipolar transistor and method of manufacturing it
In the inventive method of producing a base terminal structure for a bipolar transistor, an etch stop layer is applied on a single-crystal semiconductor...
US-7,091,083 Method for producing a capacitor
A method for producing a capacitor comprises providing a raw structure having a substrate and at least one dielectric layer, wherein a first area and a second...
US-7,091,062 Wafer level packages for chips with sawn edge protection
The invention relates to a wafer level package for chips with chip edge protection, comprising individual chips, which can in each case be mounted on a suitable...
US-7,090,967 Pattern transfer in device fabrication
A method of transferring a pattern onto a substrate, in the fabrication of ICs, is disclosed. The substrate is coated with a photoresist layer, wherein the...
US-7,090,948 Reflection mask and method for fabricating the reflection mask
A reflection mask, preferably, an EUV reflection mask, for imaging a pattern that has or is formed on the mask onto a semiconductor wafer with extreme...
US-7,089,468 Program-controlled unit and method for identifying and/or analyzing errors in program-controlled units
The program-controlled unit, during the execution of the program, can switch itself to a state in which selected elements that can be connected to form scan...
US-7,089,025 Method and device for controlling combined UMTS/GSM/EDGE radio systems
In a method for controlling radio systems designed for transmission/reception of signals based on at least two radio standards with different time patterns, with...
US-7,088,976 Device for reconstructing data from a received data signal and corresponding transceiver
In a transceiver which is configured in particular for transmitting optical data, there is provided a device for reconstructing data from a received data signal...
US-7,088,753 Semiconductor laser structure
The active layer (1) and the barrier layers (2) contain a group III component, a group V component and nitrogen, whereby the active layer is a quaternary...
US-7,088,624 System of multiplexed data lines in a dynamic random access memory
A system of multiplexed data lines in a DRAM integrated circuit includes a switching circuit having two switching states. In one switching state, the data lines...
US-7,088,612 MRAM with vertical storage element in two layer-arrangement and field sensor
A magnetic memory element including a magnetic storage element including two magnetic layers made of magnetic material, said two magnetic layers opposing each...
US-7,088,611 MRAM with switchable ferromagnetic offset layer
A magnetoresistive memory cell includes a magnetic tunnel junction including first (fixed) and second (free) magnetic regions, where the second magnetic region...
US-7,088,160 Circuit arrangement for regulating a parameter of an electrical signal
A circuit arrangement for regulating a parameter (e.g., duty cycle) of an electrical signal, generated by a circuit component. The regulating device includes a...
US-7,088,128 Circuit module
A circuit module comprises a first circuit chip (102a) and a second circuit chip (102b). Each circuit chip comprises a signal input (104a, 104b) and a reference...
US-7,088,122 Test arrangement for testing semiconductor circuit chips
The invention relates to a test arrangement for testing semiconductor circuit chips, in which a test signal received via a primary test channel from a driver...
US-7,088,006 Integrated circuit arrangement
Integrated circuit arrangement, in which bearing areas of mutually opposing sides of a carrier and of a substrate layer, which carries circuit structures, are...
US-7,087,981 Metal semiconductor contact, semiconductor component, integrated circuit arrangement and method
The present invention relates to a metal-semiconductor contact comprising a semiconductor layer and comprising a metallization applied to the semiconductor...
US-7,087,975 Area efficient stacking of antifuses in semiconductor device
A semiconductor device is provided which is formed of a wafer having on a surface thereof an area efficient arrangement of at least two antifuses in vertically...
US-7,087,950 Flash memory cell, flash memory device and manufacturing method thereof
The present invention relates to a flash memory cell comprising a silicon substrate having an active region comprising a channel region and ...
US-7,087,938 ESD protective circuit with collector-current-controlled triggering for a monolithically integrated circuit
An ESD protective circuit protects an input or output of a monolithically integrated circuit. The ESD protective circuit has at least one bipolar transistor...
US-7,087,910 Method for detecting and compensating for positional displacements in photolithographic mask units and...
A method for detecting and compensating for positional displacements of a photolithographic mask unit, includes providing mask production data for the writing of...
US-7,087,512 Method for fabricating connection regions of an integrated circuit, and integrated circuit having connection...
A method for fabricating an integrated circuit connection region includes application of a dielectric to an integrated circuit with a connection region,...
US-7,087,502 Method for generating chip stacks
Disclosed is a method for generating chip stacks during the production of chips from wafers, the chips located on the wafer being separated from one another, the...
US-7,087,500 Charge trapping memory cell
A memory cell includes a channel region between source/drain regions at the top side of a semiconductor body and is provided, transversely with respect to the...
US-7,087,492 Method for fabricating transistors of different conduction types and having different packing densities in a...
A gate electrode layer is doped in a first section of a semiconductor substrate. By means of a patterning, encapsulated gate electrodes emerge from the gate...
US-7,087,485 Method of fabricating an oxide collar for a trench capacitor
A method for fabricating patterned ceramic layers on areas of a relief structure, wherein the layers may be arranged essentially perpendicular to a top side of a...
US-7,087,484 Method for fabricating trench capacitors for integrated semiconductor memories
In a method for fabricating trench capacitors, in particular for memory cells having at least one selection transistor for integrated semiconductor memories, a...
US-7,087,438 Encapsulation of conductive lines of semiconductor devices
The invention relates to a method of encapsulating conductive lines of semiconductor devices and a structure thereof. An encapsulating protective material, such...
US-7,085,992 Method and device for decoding a sequence of physical signals, reliability detection unit and viterbi decoding unit
A method and device for decoding a sequence of physical signals. A Viterbi algorithm is carried out a first time for all physical signals, resulting in a maximum...
US-7,085,972 System for testing a group of functionally independent memories and for replacing failing memory words
System for testing a group of functionally independent memories (102) and for replacing failing memory words of the group of functionally independent memories...
US-7,085,951 Method for generating a signal pulse sequence with a predetermined stable fundamental frequency
A method for generating a signal pulse sequence with a predetermined stable fundamental frequency from a sequence of signal pulses whose frequency fluctuates and...
US-7,085,373 Circuit and method for detecting AC voltage pulses
A detection circuit and method for detecting AC voltage pulses at a defined frequency relate to first transforming an input signal to a low-frequency signal by...
US-7,085,372 Method and device for transmitting a transmission signal via a two-core line
Method and apparatus for transmitting a transmission signal via a two-core line, in particular a telephone line, in which case, with the aid of corresponding...
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