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Patent # Description
US-7,122,434 Method for generating an electrical contact with buried track conductors
A semiconductor structure 300 comprises a plurality of first track conductors 303, a plurality of second track conductors 304, which are insulated with respect...
US-7,122,423 Method for fabricating a memory cell
The invention provides a method for fabricating a memory cell for storing electric charge, which has a substrate (101), which forms a first electrode, a...
US-7,122,400 Method of fabricating an interconnection for chip sandwich arrangements
The invention relates to an interconnection for chip sandwich structures by means of which chips can be electrically and mechanically connected to one another...
US-7,121,738 Bidirectional optical transmitting and receiving module
A bidirectional optical transmitting and receiving module for connection to an optical waveguide, having an optical receiving device and an optical transmitting...
US-7,121,138 Apparatus and method for detecting a tire deformation of a vehicle tire
An apparatus for detecting a tire deformation of a vehicle tire includes a tire pressure sensor for sensing a tire pressure, a signal processor configured to...
US-7,120,841 Data generator for generating test data for word-oriented semiconductor memories
A data generator for generating test data for a word-oriented semiconductor memory is integrated on a semiconductor chip of the semiconductor memory. The data...
US-7,120,818 Method and device for data transfer
Data transfer is effected on an internal and/or on an external transfer path with or in a semiconductor component, such as a semiconductor memory. A first...
US-7,120,660 Method of and apparatus for modular multiplication
In a method for modular multiplication using a multiplication look-ahead process for computing a multiplication shift value and a reduction look-ahead process...
US-7,120,077 Memory module having a plurality of integrated memory components
A memory module includes a plurality of integrated memory components are arranged on a mounting substrate and a refresh control circuit arranged separately from...
US-7,120,074 Semiconductor memory and method for operating a semiconductor memory
A semiconductor memory includes storage cells (2) that have storage capacitors and transistors with an electrode, which is electrically biasable with two...
US-7,120,070 Method for testing the serviceability of bit lines in a DRAM memory device
DRAM memory device (1) comprising at least one array of memory cells (2, 3, 4, 5), each memory cell (12) being connected to a bit line (BL) and a word line (WL),...
US-7,120,067 Memory with data latching circuit including a selector
A circuit for latching data into a memory includes a receiver, a delay, and a selector. The receiver is configured for receiving a data signal, and the delay is...
US-7,119,670 Tire pressure monitoring system
In the system for monitoring tire pressure in a tire of a vehicle, temporally successive tire pressure measured values are sensed by a transmitting unit, and at...
US-7,119,610 Circuit arrangement
Circuit arrangement for demodulating a voltage which is ASK modulated by alternating the amplitude between a low and a high level. Respective charging voltages...
US-7,119,608 Forward-amplifying filter circuit
The invention relates to a forward-amplifying filter circuit which has an analogue filter with poles and zero points, having a first number of integrators which...
US-7,119,567 System and method for testing one or more dies on a semiconductor wafer
A testing system or method compares read data from one or more dies in a semiconductor wafer with the original data written onto the one or more dies The testing...
US-7,119,415 Monolithically integrated circuit comprising a thin film resistor, and fabrication method thereof
A monolithically integrated circuit comprises a thin film resistor (8) with low resistance and low temperature coefficient; a high frequency lateral power...
US-7,119,399 LDMOS transistor
A semiconductor device has a semiconductor substrate, an insulating layer on top of the substrate, a lateral field effect transistor with a drain region and a...
US-7,119,395 Memory cell with nanocrystals or nanodots
The storage layer (6) is in each case present above a region in which the channel region (3) adjoins a source/drain region (2) and is in each case interrupted...
US-7,119,384 Field effect transistor and method for fabricating it
The invention relates to a field effect transistor in which the planar channel region on the upper surface of the elevation is extended in width by means of...
US-7,119,021 Ferroelectric capacitor devices and a method for compensating for damage to a capacitor caused by etching
A ferroelectric capacitor in which damage caused by etching exposed faces of a ferroelectric layer of the capacitor is compensated by depositing a seeding layer...
US-7,118,955 Method for the production of a semiconductor substrate comprising a plurality of gate stacks on a semiconductor...
Method for the production of a semiconductor structure comprising a plurality of gate stacks on a semiconductor substrate which serve as control electrodes for a...
US-7,117,414 Method for identifying an integrated circuit
An identifier is provided for an integrated circuit with a memory composed of a multiplicity of memory cells. The circuit has a manufacture-related memory cell...
US-7,117,407 Method for testing a semiconductor memory having a plurality of memory banks
A testing method involves information being written to memory addresses and being read from the memory addresses. The method which logically combines parallel...
US-7,117,404 Test circuit for testing a synchronous memory circuit
Test circuit for testing a synchronous memory circuit having a frequency multiplication circuit which multiplies a clock frequency of a low-frequency clock...
US-7,117,403 Method and device for generating digital signal patterns
The method and the device generate digital signal patterns. Signal patterns or signal pattern groups are stored in a very small buffer register. The position of...
US-7,117,343 Fetching instructions to instruction buffer for simultaneous execution with long instruction sensing or buffer...
A program-controlled unit has a plurality of instruction-execution units for simultaneously executing successive instructions of a program that is to be...
US-7,117,233 Random number generator and method for generating a random number
A random number generator includes a noise signal generating device for supplying a noise signal, a sampling device connected between an output of the noise...
US-7,116,964 Signal reception and processing method for cordless communications systems
Channel selection of a received signal is first of all carried out, in the process, by way of an analog channel selection filter. The signal is then converted to...
US-7,116,737 Apparatus for signaling that a predetermined time value has elapsed
The present invention provides an apparatus for signaling that a predetermined time value has elapsed, having a device for acquiring and storing the amplitude...
US-7,116,659 Data transmission memory
Data transmission memory (1) for the transmission of data packets between subscribers T with a pointer address memory (2) for storing chained subscriber-pointer...
US-7,116,583 Electrically programmable memory cell and methods for programming and reading from such a memory cell
The invention relates to an electrically programmable memory cell comprising a memory transistor having a source and a drain zone and also a storage electrode...
US-7,116,159 Method and apparatus for adjusting an active filter
An adjustable filter, particularly for use as an antialiasing filter in digital telecommunications networks, includes adjustable capacitors which determine...
US-7,116,148 Variable delay line using two blender delays
A variable delay line comprises a first blender delay configured to provide a first signal, a second blender delay configured to provide a second signal...
US-7,115,897 Semiconductor circuit configuration and semiconductor memory device
A semiconductor circuit configuration has at least one pair of complementary operating field-effect transistors in which each transistor has a gate region, first...
US-7,115,522 Method for manufacturing semiconductor device
A method for manufacturing a semiconductor device including a substrate to be processed having a conductive layer essentially consisting of platinum includes...
US-7,115,501 Method for fabricating an integrated circuit device with through-plating elements and terminal units
A method for fabricating an integrated circuit device, an electrically conductive substrate being provided, an insulation layer being deposited on the substrate,...
US-7,115,496 Method for protecting the redistribution layer on wafers/chips
The invention relates to a method for protecting the redistribution layer on wafers/chips, which preferably comprises a structure constructed from a seed layer,...
US-7,113,574 Integrated telephone set with an xDSL-modem
Integrated telephone with an xDSL-modem (2), comprising a splitter unit (6) for separating telephone signals received via a telephone line (9) in a low-frequency...
US-7,113,561 Clock control circuit for controlling the clock phase of a transceiver
A clock phase control circuit is provided for controlling the clock phase of a transceiver, having a sampling circuit for sampling an analog received signal with...
US-7,113,428 Method for operating a memory cell array
Prior to the reprogramming of a selected flash memory cell of a memory cell array, electrons being removed from the memory layer (M) in the channel region (C) by...
US-7,113,424 Energy adjusted write pulses in phase-change memories
A memory cell device that includes a plurality of phase-change memory cells, at least one write pulse generator, and at least one temperature sensor. The...
US-7,113,417 Integrated memory circuit
In a memory circuit integrated on a semiconductor chip, an interface system is formed between the connection pads and associated internal signal lines and...
US-7,113,024 Circuit module with high-frequency input/output interfaces
The invention relates to a circuit module with high-frequency input/output interfaces, and in particular to a circuit realized on a chip, principally a...
US-7,113,015 Circuit for setting a signal propagation time for a signal on a signal line and method for ascertaining timing...
A tuning circuit for setting a signal propagation time on a signal line in an integrated circuit, particularly a DRAM circuit, has a transistor and a capacitor....
US-7,113,010 Clock distortion detector using a synchronous mirror delay circuit
The invention refers to a clock distortion detection method, and a clock distortion detector including a first input for receiving a first clock signal, a second...
US-7,113,001 Chip to chip interface
A chip to chip interface comprises a driver configured to provide a first signal in response to a change in first data at one edge of a clock signal and a second...
US-7,112,947 Bandgap reference current source
Bandgap reference current source for generating a reference current (I.sub.REF) having: at least two bipolar transistors (T.sub.1, T.sub.2), the base terminals...
US-7,112,895 Reduced power consumption in integrated circuits with fuse controlled redundant circuits
System and method for reducing power consumption in integrated circuits (IC) with fuse controlled redundant circuits. A preferred embodiment comprises detecting...
US-7,112,868 IGBT with monolithic integrated antiparallel diode
An IGBT with monolithic integrated antiparallel diode has one or more emitter short regions forming the diode cathode in the region of the high-voltage edge. The...
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