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Patent # Description
US-7,078,748 Multi-layer gate stack structure comprising a metal layer for a FET device, and method for fabricating the same
A multi-layer gate stack structure of a field-effect transistor device is fabricated by providing a gate electrode layer stack with a polysilicon layer, a...
US-7,078,709 Apparatus and method for proof of outgassing products
Outgassing products, which are formed during the exposure of photoresist systems by laser irradiation, are adsorbed on a proof plate for further analysis.
US-7,078,325 Process for producing a doped semiconductor substrate
A process is described which allows a buried, retrograde doping profile or a delta doping to be produced in a relatively simple and inexpensive way. The process...
US-7,078,313 Method for fabricating an integrated semiconductor circuit to prevent formation of voids
Recesses between gate layer stacks are filled with a first electrically insulating material. Cavities or voids are opened up during the removal of a portion of...
US-7,078,309 Methods for producing a structured metal layer
The invention provides methods which can be used to structure even precious metal electrodes with conventional CMP steps, in particular with the aid of...
US-7,078,290 Method for forming a top oxide with nitride liner
A method for forming a top oxide for a deep trench memory device comprising a poly stud above a polysilicon fill in a deep trench and an isolation region in a...
US-7,078,135 Method for patterning a mask layer and semiconductor product
During the lithographic exposure of layers to be patterned on semiconductor products, use is made of masks whose mask pattern is imaged on a reduced scale, with...
US-7,078,134 Photolithographic mask having a structure region covered by a thin protective coating of only a few atomic...
A photolithographic mask for patterning a photosensitive material, in particular on a wafer, has at least one structure region for imaging a structure on the...
US-7,078,133 Photolithographic mask
A photolithographic mask has the advantage that a combination of dummy structures, whose pattern is imaged into the resist layer, and auxiliary structures, whose...
US-7,077,331 Chip card having a projection mirror
A chip card for generating an image projection includes a substrate, a mirror which is held movable with reference to the substrate, an actuator for moving the...
US-7,076,700 Method for reconfiguring a memory
Faulty memory cells in a plurality of memory blocks are replaced by redundant memory cells. Each block includes plurality of first and second redundant address...
US-7,076,512 Digital interpolation filter and method of operating the digital interpolation filter
A digital comb filter contains filter stages. Each filter stage has a latch disposed at a filter stage input, which latch, by outputting each input data value...
US-7,076,418 Method and device for system simulation of microcontrollers/microprocessors and corresponding peripheral modules
A method for system simulation, which is distinguished by a first sequence of steps for simulating a microcontroller/microprocessor and peripheral modules using...
US-7,075,961 Laser diode with vertical resonator and method for fabricating the diode
The invention relates to a laser diode including a vertical resonator and to a method for producing the laser diode such that at least one active layer is...
US-7,075,814 Method for homogeneously magnetizing an exchange-coupled layer system of a digital magnetic memory location device
A method and apparatus for homogeneously magnetizing an exchange-coupled layer system of a digital magnetic memory cell device comprising an AAF layer system and...
US-7,075,807 Magnetic memory with static magnetic offset field
A magnetoresistive or magnetic memory element and a magnetic random access memory having one or more magnetic memory elements. The memory element includes a...
US-7,075,148 Semiconductor memory with vertical memory transistors in a cell array arrangement with 1-2F.sup.2 cells
The invention relates to a semiconductor memory having a multiplicity of memory cells, each of the memory cells having N (e.g., four) vertical memory transistors...
US-7,075,137 Semiconductor memory having charge trapping memory cells
In a charge trapping memory architecture for virtual ground with interconnects (6) that are present parallel to the word lines (2) and STI isolations (1) that...
US-7,075,127 Single-poly 2-transistor based fuse element
An electrically programmable transistor fuse having a double-gate arrangement disposed in a single layer of polysilicon in which a first gate is disposed...
US-7,074,696 Semiconductor circuit module and method for fabricating semiconductor circuit modules
The present invention provides a method for fabricating semiconductor circuit modules having the following steps: application of a patterned connection layer to...
US-7,074,689 Method for fabricating a trench capacitor having an insulation collar, which is electrically connected to a...
The present invention provides a method for fabricating a trench capacitor having an insulation collar (10; 10a, 10b) in a substrate (1), which is electrically...
US-7,074,678 Method for fabricating a buried bit line for a semiconductor memory
In a method for fabricating a buried bit line for a semiconductor memory, the buried bit line is produced as a diffusion region using a dopant source including...
US-7,074,660 FinFet device and method of fabrication
A transistor fin of a fin field-effect transistor is arranged between two contact structures. A gate electrode encapsulating the transistor fin on three sides is...
US-7,074,649 Method for producing an integrated circuit with a rewiring device and corresponding integrated circuit
The present invention provides a method for producing an integrated circuit with a rewiring device. In the method, there is provision of a carrier device with...
US-7,074,529 Phase-shift mask
The relative surface area sizes of portions having distinct phase-shift and transmission of light of a pattern on a phase-shift mask substantially obey the...
US-7,074,528 Effective assist pattern for nested and isolated contacts
A photomask with desired illumination conditions can be constructed by combining a base pattern of openings with an assist pattern which includes openings that...
US-7,074,525 Critical dimension control of printed features using non-printing fill patterns
Non-uniformity and image shortening are substantially reduced in an image printed on a substrate using a photolithographic mask in which the mask pattern...
US-7,074,317 Method for fabricating trench capacitors for large scale integrated semiconductor memories
An electrochemical method is provided for producing trenches for trench capacitors in p-doped silicon with a very high diameter/depth aspect ratio for large...
US-7,074,072 Method of making contact with circuit units to be tested in a tester and contact-making apparatus for...
A contact-making apparatus for making contact with circuit units to be tested in a tester contains a printed circuit board device that has electrical connections...
US-7,073,969 Method for fabricating a photomask for an integrated circuit and corresponding photomask
A method for fabricating a photomask for an integrated circuit. The method includes, for example, providing a substrate with at least one trench, providing a...
US-7,073,957 Optoelectronic transmitting and/or receiving module, circuit carrier, module housing, and optical plug
An optoelectronic transmitting and/or receiving module and an optical plug include a circuit carrier disposed at least partially in an alignment parallel to the...
US-7,073,069 Apparatus and method for a programmable security processor
A digital logic circuit comprises a programmable logic device and a programmable security circuit. The programmable security circuit stores a set of authorized...
US-7,072,422 Device and method for spectrally shaping a transmission signal in a radio transmitter
A device for spectrally shaping a discrete-value transmission signal, in a radio transmitter, includes one input for receiving an in phase component of the...
US-7,072,234 Method and device for varying an active duty cycle of a wordline
A semiconductor memory is provided which is operable in at least a test mode. Such semiconductor memory includes a memory array, the memory array including a...
US-7,072,233 Method and apparatus for optimizing the functioning of DRAM memory elements
In the method for modifying a default time duration between an execution instant of a second operation and an earlier execution instant of a first operation...
US-7,071,729 Dual-purpose shift register
A serial shift register and method for simultaneously storing bits of data and a serially advancing pointer is provided. In one embodiment, each stage of the...
US-7,071,724 Wafer probecard interface
Apparatus and method for testing a device wafer having a plurality of devices formed thereon. One embodiment of the invention provides an interface wafer...
US-7,071,676 Circuit configuration and method for measuring at least one operating parameter for an integrated circuit
A circuit configuration for measuring at least one operating parameter for an integrated circuit includes an analysis circuit connected to at least one external...
US-7,071,571 Semiconductor component having a plastic housing and methods for its production
The invention relates to a semiconductor component having a plastic housing which encloses a rewiring structure which has flat conductors embedded in plastic....
US-7,071,506 Device for inhibiting hydrogen damage in ferroelectric capacitor devices
A ferroelectric capacitor device comprises a substrate, a contact plug passing through the substrate, a first electrode formed on the substrate, the first...
US-7,071,110 Process for the plasma etching of materials not containing silicon
A process enables plasma etching of materials that do not contain silicon. The process is particularly suitable for the side wall passivation of chromium layers...
US-7,071,074 Structure and method for placement, sizing and shaping of dummy structures
A material layer on a substrate being processed, e.g. to form chips, includes one or more functional structures. In order to control pattern density during...
US-7,070,904 Polybenzoxazoles from poly-o-hydroxyamide, novel poly-o-hydroxyamides, preparation processes therefor, and...
High-temperature-stable polybenzoxazoles are formed from novel poly-o-hydroxyamides. The novel poly-o-hydroxyamides have low dielectric constants, are suitable...
US-7,070,887 Photolithographic mask
A photolithographic mask is based on a combination of a half-tone phase mask and an alternating phase mask such that when radiation passes through some of the...
US-7,070,479 Arrangement and method for conditioning a polishing pad
An in-situ measurement of thickness profiles of polishing pads (1) used in chemical mechanical polishing (CMP) is enabled by arranging sensors (7) for measuring...
US-7,069,652 Method for producing laminated smart cards
A smart card is laminated from at least two layers of paper or film as a mounting material. A first of the layers is fitted with a semiconductor chip and a...
US-7,069,647 Method for populating a substrate with electronic components
A novel method and placement system are configured for populating a substrate with an electronic component. The placement system has a substrate holding device...
US-7,068,546 Integrated memory having a voltage generator circuit for generating a voltage supply for a read/write amplifier
An integrated memory contains a memory cell array, which has word lines and bit lines, and a read/write amplifier, which is connected to the bit lines for the...
US-7,068,533 Resistive memory cell configuration and method for sensing resistance values
A configuration of resistive memory cells is disclosed. In one embodiment, the configuration of resistive memory cells comprises a plurality of first current...
US-7,068,486 Half-bridge circuit and method for driving the half-bridge circuit
A half-bridge circuit has first and second semiconductor switches, which have load paths connected in series and which are driven in dependence on an input...
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