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Patent # Description
US-7,160,670 Resist for forming a structure for aligning an electron or ion beam and technique for forming the structure
A scintillating structure for aligning an electron or ion beam using a detector while exposing a wafer, which may be a wafer or mask, is described. The structure...
US-7,159,786 Data carrier card
Data carrier card having a card body of a flat form and having a recess, a carrier, a chip arranged on the carrier and inserted in the recess of the card body,...
US-7,159,157 Apparatus and method for testing a device for storing data
The present invention provides an apparatus for testing a device (102) for storing data, which has a device for comparing actual data with set point data for...
US-7,159,156 Memory chip with test logic taking into consideration the address of a redundant word line and method for...
A memory chip includes an on-chip data generator, a scrambler unit for checking the correct operability of the memory cells, a repair unit, and redundant word...
US-7,159,152 System with a monitoring device that monitors the proper functioning of the system, and method of operating...
A system and a method are distinguished by the fact that, if it is determined that the system is not operating properly, a control device is stopped and it is...
US-7,159,145 Built-in self test system and method
External test equipment is used to simulate an internal BIST test, thus enabling the capture or generation of detailed test results. By simulating the BIST test...
US-7,159,103 Zero-overhead loop operation in microprocessor having instruction buffer
A loop instruction, at least one target instruction, and an associated trigger address are cached during loop entry. During each loop iteration, the processor...
US-7,158,496 Method and device for processing a digital data signal in a CDMA radio transmitter
A digital data signal to be transmitted is split into a number of subsidiary data signals by a data signal splitting device and is output by a timeslot data...
US-7,158,434 Self-refresh circuit with optimized power consumption
A random access memory device has a memory array, and a refresh rate generator circuit. The memory array has a plurality of memory cells that are configured to...
US-7,158,426 Method for testing an integrated semiconductor memory
An integrated semiconductor memory can be operated in a normal operating state synchronously with a control clock. In the test operating state, the integrated...
US-7,158,416 Method for operating a flash memory device
An error correction code is applied and an erasing procedure is passed as accomplished, if a maximum number of single bit failures in compliance with a criterion...
US-7,158,405 Semiconductor memory device having a plurality of memory areas with memory elements
A semiconductor memory device has a particularly space-saving configuration of the memory areas and, in particular, of the selection devices assigned to the...
US-7,158,396 CAM (content addressable memory) apparatus
The present invention provides a CAM (content addressable memory) apparatus having: a first memory device (10) with a word line input (WL) and at least one...
US-7,158,361 Method and apparatus for regulating a current through an inductive load
The invention relates to a method and an apparatus for regulating a current through an inductive load, which can be connected to a power supply, to a prescribed...
US-7,158,359 Circuit configuration having a semiconductor switch and a protection circuit
A circuit configuration has a first semiconductor switch and a first protection circuit. The protection circuit has a second semiconductor switch whose load path...
US-7,158,063 High-resolution sigma-delta converter
A sigma-delta converter is disclosed. In one embodiment, the sigma-delta converter includes two series-connected converter stages which are each supplied with a...
US-7,157,970 Rail-to-rail-input buffer
A rail-to-rail-Input Buffer with constant mutual conductance includes a differential input; a first differential stage supplied with a first reference current; a...
US-7,157,923 Method for full wafer contact probing, wafer design and probe card device with reduced probe contacts
A technique to simplify the cost and complexity of performing a full wafer test or probe of semiconductor wafers. A probe card connection layer is disposed on a...
US-7,157,768 Non-volatile flash semiconductor memory and fabrication method
In a semiconductor memory, a plurality of FinFET arrangements with trapping layers or floating gate electrodes as storage mediums are present on respective top...
US-7,157,767 Semiconductor memory element, semiconductor memory arrangement, method for fabricating a semiconductor memory...
A semiconductor memory element has a substrate, in which a source region and a drain region are formed, a floating gate electrically insulated from the...
US-7,157,382 Method for expanding a trench in a semiconductor structure
The present invention provides a method for expanding a trench in a semiconductor structure. A trench is provided in a semiconductor substrate,...
US-7,157,381 Method for providing whisker-free aluminum metal lines or aluminum alloy lines in integrated circuits
A method for providing whisker-free aluminum metal lines or aluminum alloy lines in integrated circuits includes the following steps: providing a substrate;...
US-7,157,373 Sidewall sealing of porous dielectric materials
A semiconductor device and method of manufacture thereof. A porous dielectric material is deposited over a workpiece. The porous dielectric material is...
US-7,157,371 Barrier layer and a method for suppressing diffusion processes during the production of semiconductor devices
A dielectric barrier layer composed of a metal oxide is applied in thin layers with a thickness of less than 20 nanometers in the course of processing...
US-7,157,329 Trench capacitor with buried strap
A trench capacitor with improved strap is disclosed. The strap is located above the top surface of the capacitor. The top surface of the trench capacitor, which...
US-7,157,328 Selective etching to increase trench surface area
The surface area of the walls of a trench formed in a substrate is increased. A barrier layer is formed on the walls of the trench such that the barrier layer is...
US-7,157,327 Void free, silicon filled trenches in semiconductors
The present invention provides methods of producing substantially void-free trench structures. After deposition of an a-Si or polysilicon layer in a trench...
US-7,157,194 Method for exposing a substrate with a structure pattern which compensates for the optical proximity effect
In a circuit layout, a partial area is defined in a first structure pattern, which is stored electronically in a data format and represents a first lithographic...
US-7,157,190 Method for repairing a photolithographic mask, and a photolithographic mask
A method for repairing at least one defect of a light-influencing structure on a photolithographic mask with a mask substrate, in particular a quartz substrate,...
US-7,157,189 Lithographic process for reducing the lateral chromium structure loss in photomask production using chemically...
The invention relates to a process for the production of photomasks. A film of a photoresist, as used for structuring semiconductor substrates, for example a...
US-7,156,933 Configuration and method for mounting a backing film to a polish head
By applying heat and pressure to a backing film with an adhesive layer while mounting it to a polish head used for chemical mechanical polishing, inhomogeneities...
US-7,156,314 Chip card
A chip card having a contact-type interface having first loads associated therewith and capable of transmitting power and data, and a contactless interface...
US-7,154,809 Method for measuring the delay time of a signal line
A memory buffer for a memory module board which is connected via a signal line (10-i) to a plurality of memory modules (2-i) mounted on said memory module board...
US-7,154,793 Integrated memory and method for functional testing of the integrated memory
An integrated memory includes memory cells arranged in a memory cell array along word lines and bit lines. One of the bit lines can be connected to a data line...
US-7,154,773 MRAM cell with domain wall switching and field select
An MRAM cell includes a magnetic tunnel junction including first and second magnetic regions stacked in a parallel, overlying relationship and separated by a...
US-7,154,771 Method of switching an MRAM cell comprising bidirectional current generation
The present invention relates to a method of switching a magnetoresistive memory (MRAM) cell including the following steps: providing an MRAM cell having a...
US-7,154,347 Compensating method for a PLL circuit that functions according to the two-point principle, and PLL circuit...
A PLL circuit is tuned to a first frequency by using a first digital modulation signal and subsequently tuned to a second frequency by using a second digital...
US-7,154,342 Phase locked loop circuit with a tunable oscillator and an independent frequency converter and frequency counter
A phase regulating arrangement or circuit is disclosed, in which, in addition to a frequency divider, which is arranged in the feedback path of the PLL and,...
US-7,154,138 Transistor-arrangement, method for operating a transistor arrangement as a data storage element and method for...
The invention relates to a transistor arrangement having a substrate and a vertical transistor comprising: a first electrode region, a second electrode region...
US-7,154,116 Rewiring substrate strip with a number of semiconductor component positions
A rewiring substrate strip with a number of semiconductor component positions and semiconductor components, which are arranged in rows and columns on the...
US-7,153,781 Method to etch poly Si gate stacks with raised STI structure
In a process for etching poly Si gate stacks with raised STI structure where the thickness of poly Si gates at the AA and STI are different, the improvement...
US-7,153,143 Circuit carrier and production thereof
A circuit carrier includes a substrate with two oppositely arranged areas. The terminal contacts of a flat connector strip are arranged in the edge regions of...
US-7,152,461 Method and apparatus for determination of the depth of depressions which are formed in a mount substrate
The invention relates to a method for determination of the depth of depressions which are formed in a mount substrate. According to the invention, an essentially...
US-7,151,828 Circuit arrangement for the analogue suppression of echoes
A circuit arrangement for the analogue suppression of echoes, as in particular can be used in a hybrid-circuit for DSL-transmission systems, comprises a replica...
US-7,151,697 Non-volatile semiconductor memory
A non-volatile semiconductor memory includes a substrate having a substrate region, at least one word line, a plurality of non-volatile memory cells arranged in...
US-7,151,474 Controlled current source; in particular for digital/analogue converters in continuous-time sigma/delta modulators
The present invention relates to a controlled current source having a control input, in particular for digital/analogue converters in continuous-time sigma/delta...
US-7,151,462 Circuit arrangement and method for load diagnosis of a semiconductor switch
The present invention relates to a circuit arrangement and a method for load diagnosis of a switch having a first and a second load connecting terminal. A first...
US-7,151,275 Reducing the contact resistance in organic field-effect transistors with palladium contacts by using nitriles...
A semiconductor device includes a semiconductor section formed from an organic semiconductor material, a first contact for injecting charge carriers into the...
US-7,150,946 Method for the repair of defects in photolithographic masks for patterning semiconductor wafers
A method for repairing defects in a photolithographic mask for use in patterning semiconductor wafers introduces a pre-selected phase error selected to sum with...
US-7,150,796 Method of removing PECVD residues of fluorinated plasma using in-situ H.sub.2 plasma
In a method of affecting cleaning or chamber process control to remove residues of fluorinated discharges from internal PECVD chamber hardware during manufacture...
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