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Patent # Description
US-7,166,533 Phase change memory cell defined by a pattern shrink material process
One embodiment of the present invention provides a memory cell device. The memory cell device includes a first electrode, a phase-change material adjacent the...
US-7,166,393 Reflection mask for projecting a structure onto a semiconductor wafer and method for producing the mask
A reflection mask for projecting a structure onto a semiconductor wafer contains a carrier material, a layer stack for reflecting obliquely incident light and...
US-7,165,198 System for testing an integrated circuit using multiple test modes
A system for testing an integrated circuit at a plurality of locations with a plurality of test modes includes a sequence of test-mode storage devices, each of...
US-7,165,002 Test device for dynamic memory modules
A test device for dynamic memory modules is described and has an electronic test unit for generating test signals. Accordingly, the electronic test unit has at...
US-7,165,000 Method and apparatus for calibrating data-dependent noise prediction
Disclosed herein is an apparatus and method of calibrating the parameters of a Viterbi detector 138 in which each branch metric is calculated based on noise...
US-7,164,708 Line termination device for a telephone subscriber line
In the line terminating device, which is provided for transmitting and receiving narrowband low-frequency voice signals and broadband data signals at a higher...
US-7,164,613 Flexible internal address counting method and apparatus
A method of controlling an internal address counter which provides a count used in accessing a storage cell array to provide increased flexibility in the...
US-7,164,567 Device for ESD protection of an integrated circuit
A device for ESD protection of a high frequency circuit (1) of a semiconductor device comprises first (3) and second (4) p-type and first (6) and second (5)...
US-7,164,328 Direct digital amplitude modulator
Various embodiments of a direct digital amplitude modulator (DDAM) for modulating radio frequency (RF) or intermediate frequency (IF) or baseband signal with the...
US-7,164,327 Compensation of the IQ phase asymmetry in quadrature modulation and demodulation methods
A simplified compensation matrix is set up for the compensation of phase errors between the I and the Q component in data transmission systems with quadrature...
US-7,163,900 Using polydentate ligands for sealing pores in low-k dielectrics
In preferred embodiments, a polydentate pore-sealing ligand is used to seal or repair pores damaged by plasma processing. The polydentate ligand includes...
US-7,163,891 High density DRAM with reduced peripheral device area and method of manufacture
A dynamic random access memory (DRAM) structure having a distance less than 0.14 um between the contacts to silicon and the gate conductor is disclosed. In...
US-7,163,857 Buried strap contact for a storage capacitor and method for fabricating it
A buried strap contact between a trench capacitor of a memory cell and the subsequently formed selection transistor of the memory cell is fabricated such that...
US-7,163,843 Semiconductor component of semiconductor chip size with flip-chip-like external contacts, and method of...
A semiconductor component and a method for its production in semiconductor chip size, can have a semiconductor chip, which has external contacts of the...
US-7,163,660 Arrangement for taking up liquid analytes
Apparatus for taking up liquid analytes having a microtitre plate with a plurality of wells and a plurality of pipettes, as well as a pump, which is coupled to...
US-7,162,682 Method of error control coding and decoding of messages in a packet-based data transmission system
Initially the message frame comprising a header with length information, a data portion and a check sequence is expanded with gaps inserted to the data portion...
US-7,162,663 Test system and method for testing memory circuits
A first and a second memory circuit are tested in parallel. It is possible to activate the memory circuits depending on a circuit select signal, and it is...
US-7,162,382 Apparatus and method for calibrating signals
The invention is directed to a device for calibrating signals, whereby at least two signal circuits are provided for generating signals. In order to calibrate...
US-7,161,981 Decision feedback equalizing device
A decision feedback equalizer device includes a linear equalizer stage, which has at least one first digital filter with an adjustable first set of coefficients....
US-7,161,938 Network switch
According to one embodiment a network switch is disclosed. The switch includes a first media access controller (MAC) coupled to a plurality of ports and a memory...
US-7,161,869 Transmission device
A transmission device has a device for generating a signal pair and a device for generating a recovered data signal. The device for generating the signal pair is...
US-7,161,861 Sense amplifier bitline boost circuit
A current sense amplifier including clamping devices and a current mirror is configured to sense the resistance of an MTJ memory cell utilizing a bitline boost...
US-7,161,824 Method for programming a memory arrangement and programmed memory arrangement
A read-only memory arrangement and method for programming the memory arrangement are provided. The memory arrangement includes memory cells, which each have a...
US-7,161,480 In-operation test of a signal path
A device for generating a sensor signal suitable for an in-operation test of a signal path from a sensor cell to an evaluation location. The sensor cell provides...
US-7,161,418 Amplifier arrangement and method for calibrating an amplifier arrangement
An amplifier arrangement is disclosed that includes at least two series-connected, programmable amplifiers. The amplifiers each have a different amplifier step...
US-7,161,368 Semiconductor component with internal heating
The invention involves a process for heating a semi-conductor component, as well as a semi-conductor component, whereby a device for heating the semi-conductor...
US-7,161,365 Apparatus and method for making ground connection
An apparatus for enabling connection to a ground plane of a test board during the testing of contacts on the board, comprising a conductive ground plate...
US-7,161,234 Semiconductor component and production method suitable therefor
A semiconductor component has a lower semiconductor element and an upper semiconductor element. A contact-making region is provided between the lower and the...
US-7,160,781 Transistor device and methods of manufacture thereof
Methods of forming transistor devices and structures thereof are disclosed. A first dielectric material is formed over a workpiece, and a second dielectric...
US-7,160,670 Resist for forming a structure for aligning an electron or ion beam and technique for forming the structure
A scintillating structure for aligning an electron or ion beam using a detector while exposing a wafer, which may be a wafer or mask, is described. The structure...
US-7,159,786 Data carrier card
Data carrier card having a card body of a flat form and having a recess, a carrier, a chip arranged on the carrier and inserted in the recess of the card body,...
US-7,159,157 Apparatus and method for testing a device for storing data
The present invention provides an apparatus for testing a device (102) for storing data, which has a device for comparing actual data with set point data for...
US-7,159,156 Memory chip with test logic taking into consideration the address of a redundant word line and method for...
A memory chip includes an on-chip data generator, a scrambler unit for checking the correct operability of the memory cells, a repair unit, and redundant word...
US-7,159,152 System with a monitoring device that monitors the proper functioning of the system, and method of operating...
A system and a method are distinguished by the fact that, if it is determined that the system is not operating properly, a control device is stopped and it is...
US-7,159,145 Built-in self test system and method
External test equipment is used to simulate an internal BIST test, thus enabling the capture or generation of detailed test results. By simulating the BIST test...
US-7,159,103 Zero-overhead loop operation in microprocessor having instruction buffer
A loop instruction, at least one target instruction, and an associated trigger address are cached during loop entry. During each loop iteration, the processor...
US-7,158,496 Method and device for processing a digital data signal in a CDMA radio transmitter
A digital data signal to be transmitted is split into a number of subsidiary data signals by a data signal splitting device and is output by a timeslot data...
US-7,158,434 Self-refresh circuit with optimized power consumption
A random access memory device has a memory array, and a refresh rate generator circuit. The memory array has a plurality of memory cells that are configured to...
US-7,158,426 Method for testing an integrated semiconductor memory
An integrated semiconductor memory can be operated in a normal operating state synchronously with a control clock. In the test operating state, the integrated...
US-7,158,416 Method for operating a flash memory device
An error correction code is applied and an erasing procedure is passed as accomplished, if a maximum number of single bit failures in compliance with a criterion...
US-7,158,405 Semiconductor memory device having a plurality of memory areas with memory elements
A semiconductor memory device has a particularly space-saving configuration of the memory areas and, in particular, of the selection devices assigned to the...
US-7,158,396 CAM (content addressable memory) apparatus
The present invention provides a CAM (content addressable memory) apparatus having: a first memory device (10) with a word line input (WL) and at least one...
US-7,158,361 Method and apparatus for regulating a current through an inductive load
The invention relates to a method and an apparatus for regulating a current through an inductive load, which can be connected to a power supply, to a prescribed...
US-7,158,359 Circuit configuration having a semiconductor switch and a protection circuit
A circuit configuration has a first semiconductor switch and a first protection circuit. The protection circuit has a second semiconductor switch whose load path...
US-7,158,063 High-resolution sigma-delta converter
A sigma-delta converter is disclosed. In one embodiment, the sigma-delta converter includes two series-connected converter stages which are each supplied with a...
US-7,157,970 Rail-to-rail-input buffer
A rail-to-rail-Input Buffer with constant mutual conductance includes a differential input; a first differential stage supplied with a first reference current; a...
US-7,157,923 Method for full wafer contact probing, wafer design and probe card device with reduced probe contacts
A technique to simplify the cost and complexity of performing a full wafer test or probe of semiconductor wafers. A probe card connection layer is disposed on a...
US-7,157,768 Non-volatile flash semiconductor memory and fabrication method
In a semiconductor memory, a plurality of FinFET arrangements with trapping layers or floating gate electrodes as storage mediums are present on respective top...
US-7,157,767 Semiconductor memory element, semiconductor memory arrangement, method for fabricating a semiconductor memory...
A semiconductor memory element has a substrate, in which a source region and a drain region are formed, a floating gate electrically insulated from the...
US-7,157,382 Method for expanding a trench in a semiconductor structure
The present invention provides a method for expanding a trench in a semiconductor structure. A trench is provided in a semiconductor substrate,...
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