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Patent # Description
US-7,149,490 Method for transmitting signals in a communication device
Instead of transmitting signals between two individual switching circuits in a communication device via separate paths for the receive and send mode, the signals...
US-7,149,243 System and method for establishing an xdsl data transfer link
An xDSL data transfer system for data transfer includes at least one xDSL user modem connected via a data transfer medium to a corresponding xDSL modem within a...
US-7,149,134 Memory device with column select being variably delayed
A memory device (10) includes an array (12) of memory cells arranged in rows and columns. Preferably, each memory cell includes a pass transistor coupled to a...
US-7,149,105 Magnetic tunnel junctions for MRAM devices
Methods of manufacturing MTJ memory cells and structures thereof. A diffusion barrier is disposed between an anti-ferromagnetic layer and a pinned layer of an...
US-7,148,834 Analog/digital converter and method for operating an analog/digital converter
The invention provides a clocked analog/digital converter for successive approximation which is designed using a jointly used amplifier and a dynamic range...
US-7,148,741 Current supply circuit and method for supplying current to a load
A current supply circuit includes an input, a load terminal, a selectively activatable current regulator, a selectively activatable adjustable current source,...
US-7,148,736 Power switch
The power switch has a first transistor, a limiting transistor, and an auxiliary transistor. The first transistor has a load path and a control electrode. The...
US-7,148,731 Duty cycle correction
A duty cycle correction circuit comprises an averaging circuit configured to receive a first signal and a second signal and provide a third signal, a duty...
US-7,148,729 Delay locked loop using synchronous mirror delay
A delay locked loop comprises a circuit configured to receive a clock signal, divide the clock signal by two to provide a divided clock signal, and mirror with...
US-7,148,539 Semiconductor structure having a compensated resistance in the LDD area and method for producing the same
A semiconductor structure includes a substrate, a source area formed in the substrate and a drain area formed in the substrate and comprising a doping of a first...
US-7,146,471 System and method for variable array architecture for memories
A memory system that employs simultaneous activation of at least two dissimilar memory arrays, during a data manipulation, such as read or write operations is...
US-7,146,456 Memory device with a flexible reduced density option
A dynamic random access memory device is capable of converting from a full density memory device to a reduced density memory device. The reduced density memory...
US-7,145,807 Method for operating an electrical writable and erasable memory cell and a memory device for electrical memories
A method is provided for operating an electrical writable and erasable memory cell, which has a channel region that can be operated in a first and a second...
US-7,145,483 Chip to chip interface for encoding data and clock signals
A chip to chip interface comprises a driver configured to receive a data signal and provide an output signal at a first level in response to receiving an odd...
US-7,145,388 Control loop having an amplifier arrangement
A control loop having an amplifier arrangement that has a variable gain is specified. The amplifier has an output for outputting a signal representing the...
US-7,145,377 Device and method for converting an input signal
A device for converting an input signal having a bipolar pulse with a positive part and a negative part of same duration, into a difference signal includes a...
US-7,145,375 Duty cycle detector with first, second, and third values
A duty cycle detector comprising a first circuit configured to receive clock cycles including a first level and a second level. The first circuit is configured...
US-7,145,369 Output driver for an integrated circuit and method for driving an output driver
One embodiment of the invention provides an output driver for an integrated circuit. The output driver has a driver circuit for driving an input signal onto an...
US-7,145,216 Antifuse programming with relaxed upper current limit
An antifuse apparatus includes first and second independent current paths connected to an antifuse. One of the current paths can be used to program the antifuse,...
US-7,145,201 Semiconductor component
A semiconductor component (10) is proposed in which a control resistance element (NTC) is provided in electrical contact between a control region (G) for setting...
US-7,145,183 Method for producing a vertically emitting laser
The invention is directed to a vertically emitting laser and a method of manufacturing such a laser having a current aperture and a semiconductor relief. The...
US-7,144,820 Method of manufacturing a layer sequence and a method of manufacturing an integrated circuit
A method of manufacturing a layer sequence having a first and a second laterally confined structure comprises the steps of providing a first layer on a first...
US-7,144,776 Charge-trapping memory device
An oxidized region is arranged between a substrate of semiconductor material and a nitride liner, which covers wordline stacks of a memory cell array and...
US-7,144,770 Memory cell and method for fabricating it
The invention provides a method for fabricating a memory cell, a substrate (101) being provided, a trench-type depression (102) being etched into the substrate...
US-7,143,390 Method for creating alternating phase masks
A method is provided for creating a phase mask for lithographic exposure operations. In this case, phase-shifting regions (10) with a different phase are defined...
US-7,143,325 Method for testing circuit units to be tested by means of majority decisions and test device for performing the...
The invention provides a test device for testing circuit units (101a 101n) to be tested, having connecting units (106a 106n) for connecting the circuit units...
US-7,143,266 Storing immediate data of immediate instructions in a data table
An efficient coding scheme is disclosed. The coding provides for the separation of immediate data from the instruction stream. A static flow analysis determines...
US-7,143,183 Server module for modularly designed server
A server module for a modularly designed server (1) having at least one data processing unit (17) for data processing data packets, at least one addressable...
US-7,142,880 Method of increasing the data throughput in a communication system
Data throughput is increased in a communication system that is designed for a bidirectional information exchange between a single master terminal unit and a...
US-7,142,478 Clock stop detector
A clock stop detector for a memory comprises a first switch that closes in response to a first logic level of a clock signal to charge a capacitor, a second...
US-7,142,473 Semiconductor device having semiconductor memory with sense amplifier
A semiconductor device comprises a memory cell array, bit line, /bit line complementary to the bit line, reference voltage generating circuit and sense...
US-7,142,143 Time-continuous sigma/delta analog-to-digital converter
Time-continuous sigma/delta analog-to-digital converter for converting an analog input signal into a digital output signal (D), having at least one analog filter...
US-7,142,070 Two-point modulator arrangement
A two-point modulator arrangement is specified, said arrangement being developed with respect to conventional two-point modulators to the effect that the...
US-7,142,069 Method and circuit arrangement for amplitude regulation of an oscillator signal
A circuit arrangement for controlling an amplitude of an oscillator signal is accomplished by comparing the oscillator signal to reference signals. The amplitude...
US-7,142,063 Two-point modulator comprising a PLL circuit and a simplified digital pre-filtering system
A two-point modulator includes a PLL circuit and a simplified digital pre-filtering system. The two-point modulator includes a first circuit path for impressing...
US-7,142,059 Amplifier arrangement
The invention provides an amplifier arrangement which is of multistage design. The output transistor in the output stage has a coupling path between its control...
US-7,142,038 Selection circuit
A selection circuit having a comparator with comparator inputs connected to first and second voltage inputs), respectively, and a comparator output connected to...
US-7,141,845 DRAM cell array and memory cell arrangement having vertical memory cells and methods for fabricating the same
Memory cells each having a cell capacitor and a cell transistor, which are arranged in a vertical cell structure, are provided in the cell array of a DRAM. By...
US-7,141,507 Method for production of a semiconductor structure
A method for producing a semiconductor structure including preparing a semiconductor substrate, and generating a lower first, a middle second and an upper third...
US-7,141,479 Bipolar transistor and method for producing the same
A method for producing a bipolar transistor is described, which comprises providing a layer sequence, which comprises a substrate, a first oxide layer and a SOI...
US-7,141,338 Sub-resolution sized assist features
Corner rounding and image shortening is substantially reduced in an image printed on a substrate by illuminating a photolithographic mask and projecting light...
US-7,140,547 Data storage configuration having a display device
A portable data storage configuration has a card base and a display device, the display device being fixed to the card base. The display device is only partially...
US-7,139,943 Method and apparatus for providing adjustable latency for test mode compression
An integrated circuit includes a core memory array and a test mode compression circuit. The test mode compression circuit receives test mode data from the core...
US-7,139,341 Receiver circuit for a communications terminal and method for processing signals in a receiver circuit
A receiver circuit for a communications terminal includes a signal pre-processing circuit having: an analog/digital converter device with K analog/digital...
US-7,139,310 Method for transmitting data streams, and warm start sequence for S(H)DSL transmission/reception devices
The invention relates to a method for transmitting data streams where transmission/reception devices (LTU, NTU) deactivated to a standby state are activated by...
US-7,139,305 Configurable terminal engine
A configurable cellular terminal engine (CTE) in accordance with an exemplary embodiment of this invention is configurable by an external agent (e.g.,...
US-7,139,290 Transmitting data into a memory cell array
A method for transmitting a data stream from a circuit unit to a memory cell array includes receiving the data stream and demultiplexing it in response to a...
US-7,139,245 Priority handling of voice over data in a voice-over-internet protocol processor
An apparatus for processing packets in a multimedia terminal has a media access controller to send and receive packets from a network. A digital signal processor...
US-7,139,206 Memory component with improved noise insensitivity
A memory component comprises a memory cell array, signal inputs, input amplifiers connected to respective ones of the signal inputs, for receiving, amplifying...
US-7,139,184 Memory cell array
A memory cell array includes memory cells, bit lines running along a first direction, word lines running along a second direction perpendicular to the first...
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