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Patent # Description
US-7,208,827 Encasing arrangement for a semiconductor component
A semiconductor component package configuration includes a semiconductor chip mounted to a printed circuit board, and a substrate arranged between the...
US-7,208,823 Semiconductor arrangement comprising transistors based on organic semiconductors and non-volatile read-write...
A semiconductor arrangement is disclosed, having transistors based on organic semiconductors and non-volatile read/write memory cells. The invention relates to a...
US-7,208,814 Resistive device and method for its production
A resistive device includes a resistive region of a semiconductor material that includes a first region and a second region, wherein the first region has a...
US-7,208,794 High-density NROM-FINFET
Semiconductor memory having memory cells, each including first and second conductively-doped contact regions and a channel region arranged between the latter,...
US-7,208,782 Reduction of the contact resistance in organic field-effect transistors with palladium contacts by using...
A semiconductor device includes a semiconductor path, the semiconductor path including an organic semiconductor material, a first contact to inject charge...
US-7,208,416 Method of treating a structured surface
The invention provides a simple method of treating a structured surface comprising a higher surface in a first region and a lower surface in the second region. A...
US-7,208,373 Method of forming a memory cell array and a memory cell array
A method of forming a memory cell array comprising a plurality of memory cells, each of the memory cells including a trench capacitor and a transistor is...
US-7,208,370 Method for fabricating a vertical transistor in a trench, and vertical transistor
To fabricate a vertical transistor, a trench is provided, the side wall of which is formed by a semiconductor substrate in single crystal form and the base of...
US-7,208,345 Method of manufacturing a semiconductor device comprising stacked chips and a corresponding semiconductor device
A first reconstituted wafer is formed, followed by a first redistribution layer. In parallel, a second reconstituted wafer is formed. The second reconstituted...
US-7,208,095 Method for fabricating bottom electrodes of stacked capacitor memory cells and method for cleaning and drying a...
Bottom electrodes of stacked capacitor DRAM cells are formed by depositing a metal layer on the side walls of trenches within a hard mask layer, which serves as...
US-7,207,030 Method for improving a simulation model of photolithographic projection
A method is provided for improving a photolithographic simulation model of the photolithographic simulation of a pattern formed on a photomask. Proceeding from a...
US-7,207,016 Method for classifying errors in the layout of a semiconductor circuit
A method for classifying errors in the layout of a semiconductor circuit includes examining the layout of the semiconductor circuit for infringement of...
US-7,206,985 Method and apparatus for calibrating a test system for an integrated semiconductor circuit
A method and an apparatus provides for calibrating a test system for an integrated semiconductor circuit, a pattern generator of the test system generating a...
US-7,206,980 Integrated semiconductor memory
An integrated semiconductor memory includes a memory cell array with at least one memory cell, in which a data value is stored, and an evaluation circuit with a...
US-7,206,978 Error detection in a circuit module
A circuit module has a module board and a plurality of circuit chips that are arranged on the module board. A module main bus having a plurality of lines of the...
US-7,206,926 Programmable unit including program operation unit and associated stopping device
A programmable unit is described having one or more program running units for running a program, with at least one of the program running units having an...
US-7,206,712 Test apparatus and test method for mixed-signal semiconductor components
A semiconductor component is tested by providing a tester, a loadboard and an evaluation apparatus. The semiconductor component is operated using a test...
US-7,206,248 Voltage booster device for semi-conductor components
A semi-conductor component (1), in particular a memory component, with at least one voltage booster, which makes available an appropriate boosted voltage (VPP,...
US-7,206,245 Methods and apparatus for implementing standby mode in a random access memory
A memory device includes: a generator system having a number of generators that supply voltage or current to the memory device, a controller that supplies to the...
US-7,206,238 Integrated semiconductor memory comprising at least one word line and method
A semiconductor memory and a test method for testing whether word line segments (12) are floating after an activation operation or a deactivation operation is...
US-7,205,849 Phase locked loop including an integrator-free loop filter
A phase locked loop PLL having a forward path and a feedback path is disclosed. A phase detector drives an oscillator in the forward path of the phase locked...
US-7,205,845 Amplifier circuit for converting the current signal from an optical receiving element into a voltage signal
An amplifier circuit for converting the current signal from an optical receiving element into a voltage signal. The amplifier circuit includes a transimpedance...
US-7,205,829 Clocked standby mode with maximum clock frequency
A method and apparatus for controlling a voltage generator of a memory device are provided. In one embodiment, a first clock signal and a second clock signal are...
US-7,205,639 Semiconductor devices with rotated substrates and methods of manufacture thereof
Integrated circuits are oriented on a substrate at an angle that is rotated between 0 to 45 degrees from a direction parallel or perpendicular to a preferred...
US-7,205,596 Adiabatic rotational switching memory element including a ferromagnetic decoupling layer
A magnetoresistive memory element includes a stacked structure with a ferromagnetic reference region including a fixed magnetization; a ferromagnetic free region...
US-7,205,581 Thyristor structure and overvoltage protection configuration having the thyristor structure
A thyristor structure having a first terminal, formed as a first region with a first conductivity type, is provided. A second region of a second conductivity...
US-7,205,567 Semiconductor product having a semiconductor substrate and a test structure and method
A semiconductor product having a test structure, in which a contact connection short-circuits that source/drain region of a transistor which is connected to an...
US-7,205,243 Process for producing a mask on a substrate
To produce a mask, a first mask layer (40) is applied to the substrate (10). During or after the deposition of the first mask layer (40), the latter is exposed...
US-7,205,195 Method for fabricating NROM memory cells with trench transistors
An electrically conductive bit line layer is applied and patterned into portions arranged parallel to one another before the trench is etched into the...
US-7,204,068 Packaging system with a tool for enclosing electronic components and method of populating a carrier tape
The invention relates to a packaging system having a tool for inserting electronic components into a carrier tape, which has passage openings. The tool has a...
US-7,203,883 Integrated circuit
An integrated semiconductor memory, which can be operated in a normal operating state and a test operating state, includes a current pulse circuit with an input...
US-7,203,859 Variable clock configuration for switched op-amp circuits
A clock configuration for driving switched op-amp circuits operated in opposite phases is presented in which a common off-phase of variable length is inserted...
US-7,203,618 Method and device for adjusting a determination rule of an angle sensor
A method for adjusting a determination rule for an error compensation of an angle sensor is designed to detect a first component of a direction along a first...
US-7,203,466 Transmitting and receiving unit
A transmitting and receiving unit includes a receiving branch and a transmitting branch that are in each case constructed for conducting complex signals, with a...
US-7,203,127 Apparatus and method for dynamically controlling data transfer in memory device
Methods and apparatus for operating a secondary sense amplifier according to different timings. Embodiments of the invention generally provide a secondary sense...
US-7,203,123 Integrated DRAM memory device
An integrated memory device including a number of memory blocks including memory cells wherein the memory cells are arranged in a matrix of wordlines and...
US-7,203,106 Integrated semiconductor memory with redundant memory cells
An integrated semiconductor memory has regular row and column lines, which can be replaced with redundant row and column lines in the event of a fault. Following...
US-7,203,102 Semiconductor memory having tri-state driver device
A semiconductor memory having at least one memory cell adapted to store a data value, and adapted to be connected to a data line through a switch device...
US-7,203,096 Method and apparatus for sensing a state of a memory cell
A cell arrangement comprising a memory cell arranged in parallel to a first capacitor is charged to a first voltage potential. A second capacitor is charged to a...
US-7,202,718 Error-compensated charge pump circuit, and method for producing an error-compensated output current from a...
A charge pump circuit has a charge pump having at least two switched current sources arranged in series. The difference between the currents produced in the two...
US-7,202,547 Capacitor with a dielectric including a self-organized monolayer of an organic compound
A capacitor is formed that includes a self-organized monolayer of an organic compound between two electrodes.
US-7,202,545 Memory module and method for operating a memory module
A memory module has an electronic printed circuit board and a plurality of semiconductor memory chips. A series circuit of the semiconductor memory chips is...
US-7,202,535 Manufacturing method for an integrated semiconductor structure and corresponding integrated semiconductor structure
The present invention provides a manufacturing method for an integrated semiconductor structure and a corresponding integrated semiconductor structure. The...
US-7,202,529 Field effect transistor
A field effect transistor includes a substrate having a doping of a first conductivity type, a drain area in the substrate having a doping of a second...
US-7,202,527 MOS transistor and ESD protective device each having a settable voltage ratio of the lateral breakdown voltage...
A MOS transistor includes a drain zone, a source zone, and a gate electrode. Doping atoms of the first conductivity type are implanted in the region of the drain...
US-7,202,107 Method for producing a semiconductor component with a plastic housing and carrier plate for performing the method
A process for producing a semiconductor component having a plastic housing in which at least one semiconductor chip is arranged includes providing a ...
US-7,201,634 Polishing methods and apparatus
Apparatus for and methods of chemical mechanical polishing (CMP) of semiconductor wafers are disclosed. A preferred embodiment comprises an apparatus for...
US-7,200,629 Apparatus and method for Fast Hadamard Transforms
A Fast Hadamard Transform generator serially performs a Fast Hadamard Transform of a sampled signal from a first channel. The Fast Hadamard Transform generator...
US-7,200,042 Method and circuit arrangement for reading from a flash/EEPROM memory cell
The invention is based on a method for reading out the content of a flash/EEPROM memory cell, in which a read current flowing via a read-out path with a memory...
US-7,200,033 MRAM with coil for creating offset field
An MRAM memory chip includes a plurality of magnetoresistive memory cells each including a magnetic tunnel junction having first (fixed) and second (free)...
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