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Zero-overhead loop operation in microprocessor having instruction buffer
A loop instruction, at least one target instruction, and an associated trigger address are cached during loop entry. During each loop iteration, the processor...
Method and device for processing a digital data signal in a CDMA radio
A digital data signal to be transmitted is split into a number of subsidiary data signals by a data signal splitting device and is output by a timeslot data...
Self-refresh circuit with optimized power consumption
A random access memory device has a memory array, and a refresh rate generator circuit. The memory array has a plurality of memory cells that are configured to...
Method for testing an integrated semiconductor memory
An integrated semiconductor memory can be operated in a normal operating state synchronously with a control clock. In the test operating state, the integrated...
Method for operating a flash memory device
An error correction code is applied and an erasing procedure is passed as accomplished, if a maximum number of single bit failures in compliance with a criterion...
Semiconductor memory device having a plurality of memory areas with memory
A semiconductor memory device has a particularly space-saving configuration of the memory areas and, in particular, of the selection devices assigned to the...
CAM (content addressable memory) apparatus
The present invention provides a CAM (content addressable memory) apparatus having: a first memory device (10) with a word line input (WL) and at least one...
Method and apparatus for regulating a current through an inductive load
The invention relates to a method and an apparatus for regulating a current through an inductive load, which can be connected to a power supply, to a prescribed...
Circuit configuration having a semiconductor switch and a protection
A circuit configuration has a first semiconductor switch and a first protection circuit. The protection circuit has a second semiconductor switch whose load path...
High-resolution sigma-delta converter
A sigma-delta converter is disclosed. In one embodiment, the sigma-delta converter includes two series-connected converter stages which are each supplied with a...
A rail-to-rail-Input Buffer with constant mutual conductance includes a differential input; a first differential stage supplied with a first reference current; a...
Method for full wafer contact probing, wafer design and probe card device
with reduced probe contacts
A technique to simplify the cost and complexity of performing a full wafer test or probe of semiconductor wafers. A probe card connection layer is disposed on a...
Non-volatile flash semiconductor memory and fabrication method
In a semiconductor memory, a plurality of FinFET arrangements with trapping layers or floating gate electrodes as storage mediums are present on respective top...
Semiconductor memory element, semiconductor memory arrangement, method for
fabricating a semiconductor memory...
A semiconductor memory element has a substrate, in which a source region and a drain region are formed, a floating gate electrically insulated from the...
Method for expanding a trench in a semiconductor structure
The present invention provides a method for expanding a trench in a semiconductor structure. A trench is provided in a semiconductor substrate,...
Method for providing whisker-free aluminum metal lines or aluminum alloy
lines in integrated circuits
A method for providing whisker-free aluminum metal lines or aluminum alloy lines in integrated circuits includes the following steps: providing a substrate;...
Sidewall sealing of porous dielectric materials
A semiconductor device and method of manufacture thereof. A porous dielectric material is deposited over a workpiece. The porous dielectric material is...
Barrier layer and a method for suppressing diffusion processes during the
production of semiconductor devices
A dielectric barrier layer composed of a metal oxide is applied in thin layers with a thickness of less than 20 nanometers in the course of processing...
Trench capacitor with buried strap
A trench capacitor with improved strap is disclosed. The strap is located above the top surface of the capacitor. The top surface of the trench capacitor, which...
Selective etching to increase trench surface area
The surface area of the walls of a trench formed in a substrate is increased. A barrier layer is formed on the walls of the trench such that the barrier layer is...
Void free, silicon filled trenches in semiconductors
The present invention provides methods of producing substantially void-free trench structures. After deposition of an a-Si or polysilicon layer in a trench...
Method for exposing a substrate with a structure pattern which compensates
for the optical proximity effect
In a circuit layout, a partial area is defined in a first structure pattern, which is stored electronically in a data format and represents a first lithographic...
Method for repairing a photolithographic mask, and a photolithographic
A method for repairing at least one defect of a light-influencing structure on a photolithographic mask with a mask substrate, in particular a quartz substrate,...
Lithographic process for reducing the lateral chromium structure loss in
photomask production using chemically...
The invention relates to a process for the production of photomasks. A film of a photoresist, as used for structuring semiconductor substrates, for example a...
Configuration and method for mounting a backing film to a polish head
By applying heat and pressure to a backing film with an adhesive layer while mounting it to a polish head used for chemical mechanical polishing, inhomogeneities...
A chip card having a contact-type interface having first loads associated therewith and capable of transmitting power and data, and a contactless interface...
Method for measuring the delay time of a signal line
A memory buffer for a memory module board which is connected via a signal line (10-i) to a plurality of memory modules (2-i) mounted on said memory module board...
Integrated memory and method for functional testing of the integrated
An integrated memory includes memory cells arranged in a memory cell array along word lines and bit lines. One of the bit lines can be connected to a data line...
MRAM cell with domain wall switching and field select
An MRAM cell includes a magnetic tunnel junction including first and second magnetic regions stacked in a parallel, overlying relationship and separated by a...
Method of switching an MRAM cell comprising bidirectional current
The present invention relates to a method of switching a magnetoresistive memory (MRAM) cell including the following steps: providing an MRAM cell having a...
Compensating method for a PLL circuit that functions according to the
two-point principle, and PLL circuit...
A PLL circuit is tuned to a first frequency by using a first digital modulation signal and subsequently tuned to a second frequency by using a second digital...
Phase locked loop circuit with a tunable oscillator and an independent
frequency converter and frequency counter
A phase regulating arrangement or circuit is disclosed, in which, in addition to a frequency divider, which is arranged in the feedback path of the PLL and,...
Transistor-arrangement, method for operating a transistor arrangement as a
data storage element and method for...
The invention relates to a transistor arrangement having a substrate and a vertical transistor comprising: a first electrode region, a second electrode region...
Rewiring substrate strip with a number of semiconductor component
A rewiring substrate strip with a number of semiconductor component positions and semiconductor components, which are arranged in rows and columns on the...
Method to etch poly Si gate stacks with raised STI structure
In a process for etching poly Si gate stacks with raised STI structure where the thickness of poly Si gates at the AA and STI are different, the improvement...
Circuit carrier and production thereof
A circuit carrier includes a substrate with two oppositely arranged areas. The terminal contacts of a flat connector strip are arranged in the edge regions of...
Method and apparatus for determination of the depth of depressions which
are formed in a mount substrate
The invention relates to a method for determination of the depth of depressions which are formed in a mount substrate. According to the invention, an essentially...
Circuit arrangement for the analogue suppression of echoes
A circuit arrangement for the analogue suppression of echoes, as in particular can be used in a hybrid-circuit for DSL-transmission systems, comprises a replica...
Non-volatile semiconductor memory
A non-volatile semiconductor memory includes a substrate having a substrate region, at least one word line, a plurality of non-volatile memory cells arranged in...
Controlled current source; in particular for digital/analogue converters
in continuous-time sigma/delta modulators
The present invention relates to a controlled current source having a control input, in particular for digital/analogue converters in continuous-time sigma/delta...
Circuit arrangement and method for load diagnosis of a semiconductor
The present invention relates to a circuit arrangement and a method for load diagnosis of a switch having a first and a second load connecting terminal. A first...
Reducing the contact resistance in organic field-effect transistors with
palladium contacts by using nitriles...
A semiconductor device includes a semiconductor section formed from an organic semiconductor material, a first contact for injecting charge carriers into the...
Method for the repair of defects in photolithographic masks for patterning
A method for repairing defects in a photolithographic mask for use in patterning semiconductor wafers introduces a pre-selected phase error selected to sum with...
Method of removing PECVD residues of fluorinated plasma using in-situ
In a method of affecting cleaning or chamber process control to remove residues of fluorinated discharges from internal PECVD chamber hardware during manufacture...
System for interchanging data between at least two contactless data
System for interchanging data between at least two contactless data storage media, particularly contactless chip cards, wherein at least one of the contactless...
Sealed capacitive sensor for physical measurements
A capacitive-type sensor comprises a glass plate having an electrode formed thereon, and a micromachined structure formed from a semiconductor material and...
Method of testing the data exchange functionality of a memory
Method of testing the functionality of a memory which operates at a high operating clock frequency, the method specifically having the following steps,...
Configurable real-time trace port for embedded processors
An embedded processor having a programmable trace port that selectively limits the amount of trace information passed from the processor core to an output...
Method and circuit for allocating memory arrangement addresses
Methods and apparatus for allocating memory arrangement addresses to a buffer chip, during an initialization mode, for use in addressing one or more memory...
Detecting usable frequency channels by exploiting complex polyphase filter
A circuit arrangement for detecting a usable frequency channel includes first and second devices for performing frequency conversion. The first and second...