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Patent # Description
US-7,236,403 Precharge arrangement for read access for integrated nonvolatile memories
Precharge arrangement for read access for integrated nonvolatile memories having at least one memory cell (2), at least one source line (8), at least one bit...
US-7,236,378 Signal distribution to a plurality of circuit units
A device for distributing a signal, in particular a clock signal or a command/address signal from a signal source to a plurality of circuit units, includes a...
US-7,236,029 Flip-flop circuit arrangement and method for processing a signal
A flip-flop circuit arrangement and an associated method are disclosed, wherein a changeover between a master and a slave block is not effected by switching on...
US-7,235,873 Protective device for subassemblies and method for producing a protective device
A protective device for subassemblies having a substrate and at least one component to be protected which is disposed on the substrate includes at least one...
US-7,235,859 Arrangement and process for protecting fuses/anti-fuses
An arrangement for protecting fuses/anti-fuses on chips which serve to activate redundant circuits or chip functions includes a passivation layer (e.g., hard...
US-7,235,822 Transistor with silicon and carbon layer in the channel region
A transistor and method of manufacturing thereof having stressed material layers formed in the channel to increase the speed and improve performance of the...
US-7,235,485 Method of manufacturing semiconductor device
Provided is a method of manufacturing a semiconductor device with enhanced electrical characteristics. The method includes disposing a substrate on a substrate...
US-7,235,472 Method of making fully silicided gate electrode
A method of making a semiconductor device for an integrated circuit chip. An interim gate electrode stack formed includes a top silicon portion patterned from a...
US-7,235,454 MIM capacitor structure and method of fabrication
A method of forming a metal-insulator-metal (MIM) capacitor wherein a plate of a MIM capacitor is formed in the entire thickness of a metallization layer of a...
US-7,235,447 Fabrication method for a semiconductor structure and corresponding semiconductor structure
The present invention provides a fabrication method for a semiconductor structure and a corresponding semiconductor structure. The fabrication method comprises...
US-7,234,360 TMR sensor
A sensor for measuring mechanical changes in length, in particular a compressive and/or tensile stress sensor, includes a sandwich system with two flat and...
US-7,234,237 Method for producing a protective cover for a device
In a method for producing a protective cover for a device formed in a substrate, at first a sacrificial structure is produced on the substrate, wherein the...
US-7,234,048 Method for initializing or configuring an electrical circuit
A method for initializing or configuring an electrical circuit, is described. The method includes reading data units stored in a memory device, using data...
US-7,233,810 Dynamically reconfigurable universal transmitter system
A dynamically reconfigurable universal transmitter system is disclosed herein. The electronic device includes multiple transmitter resources for generating...
US-7,233,618 Circuit configuration and method for transmitting digital signals
To transmit digital signals, binary signals are transformed into a series of pulses, the pulses being modulated in their pulse length as a function of an...
US-7,233,515 Integrated memory arrangement based on resistive memory cells and production method
An integrated memory arrangement based on resistive memory cells that can be changed over between a first state of high electrical resistance and a second state...
US-7,233,514 Non-volatile semiconductor memory and method for reading a memory cell
A method for reading a memory cell, wherein the memory cell comprises two source/drain regions and a gate, wherein the source/drain regions are each connected to...
US-7,233,288 Receiver for a position-finding system with improved sensitivity
A receiver (1) of a position-finding system comprises a calculation unit (6, 7, 8) for calculation of a statistical value (.LAMBDA.) on the basis of a received...
US-7,233,224 Component arrangement with a planar transformer
The invention relates to a component arrangement which has the following features: a semiconductor body (10), a dielectric layer (20) which is applied to one...
US-7,233,161 Integrated circuit and associated packaged integrated circuit having an integrated marking apparatus
An integrated circuit and an associated packaged integrated circuit are provided which improve testability and reduce the test costs. The integrated circuit...
US-7,233,059 Semiconductor arrangement
The invention relates to a vertical arrangement of at least two semiconductor components which are electrically insulated from one another by at least one...
US-7,233,053 Integrated semiconductor product with metal-insulator-metal capacitor
To fabricate an integrated semiconductor product with integrated metal-insulator-metal capacitor, first of all a dielectric auxiliary layer (6) is deposited on a...
US-7,233,031 Vertical power semiconductor component
A vertical power semiconductor component, e.g. a diode or an IGBT, in which there are formed, on the rear side of a substrate, a rear side emitter or a cathode...
US-7,232,722 Method of making a multibit non-volatile memory
The present invention relates to a method of making a multibit non-volatile memory and especially to a method of making a flash memory such as a...
US-7,232,264 Optoelectronic arrangement having a laser component, and a method for controlling the emitted wavelength of a...
The invention relates to an optoelectronic arrangement having a laser component. There are provided: a cooling device of small design for cooling the laser...
US-7,231,562 Memory module, test system and method for testing one or a plurality of memory modules
The invention relates to an integrated memory module having a memory unit and a self-test circuit, the self-test circuit being embodied in such a way as to make...
US-7,231,488 Self-refresh system and method for dynamic random access memory
A system and method are provided for reducing a rate for refreshing a portion of a dynamic random access memory (DRAM). The method includes storing a information...
US-7,231,352 Method for computer-supported speech recognition, speech recognition system and control device for controlling...
The speech recognition rate which is necessary is determined for a selected speech recognition application. The information content of the feature vector...
US-7,231,325 System for evaluating a sensor signal
The inventive device for evaluating the sensor signal includes the provider for providing the sensor signal, the processor for processing the sensor signal and...
US-7,231,215 Method and a central control unit for channel switching in a packet-based wireless communication network
In a packet-based communication network a central control unit indicates its presence on the first channel by in addition to data traffic transmits regular...
US-7,230,978 Channel CODEC processor configurable for multiple wireless communications standards
A reconfigurable channel CODEC (encoder and decoder) processor for a wireless communication system is disclosed. A high degree of user programmability and...
US-7,230,877 Method of making a semiconductor memory device
A method for fabricating a semiconductor memory device is described. An insulating layer is disposed on a semiconductor substrate. A matrix of semiconductor...
US-7,230,858 Dual frequency first-in-first-out structure
Techniques and circuitry for transferring data from memory arrays of a memory device to output pins via a FIFO structure are provided. Input and output stages of...
US-7,230,831 Heat sink for surface-mounted semiconductor devices
A heat sink is arranged on a main circuit board of an electronic module. The heat sink includes a three-dimensionally structured thermally conductive plate with...
US-7,230,559 Quantizer in a multilevel sigma-delta analogue/digital converter
The quantizer (2') has an input network (5) which generates N different drive signals (V.sub.ij) as a function of the quantizer input signal (V.sub.I+-V.sub.I-)....
US-7,230,490 Voltage to current converter and method for converting
A voltage to current converter comprises a signal stage (1) with a first transistor (11) and a first resistor (12). The first transistor (11) is adapted to be...
US-7,230,465 Duty cycle corrector
A duty cycle corrector comprising a first circuit and a second circuit. The first circuit is configured to receive a clock signal having a first phase and a...
US-7,230,462 Clock signal synchronizing device, and clock signal synchronizing method
The invention relates to a clock signal synchronizing method, and to a clock signal synchronizing device for synchronizing clock signals. In particular the...
US-7,230,458 Delta/sigma frequency discriminator
Delta/sigma frequency discriminator (1) for converting a frequency (F.sub.v) of an input signal into a digital output signal (C) comprising a frequency divider...
US-7,230,442 Semi-conductor component testing process and system for testing semi-conductor components
The invention involves a semi-conductor component testing process, and a system for testing semi-conductor components, in which a central computer device, in...
US-7,230,309 Semiconductor component and sensor component for data transmission devices
The invention relates to a semiconductor component and a sensor component with data transmission devices, for wireless transmission the semiconductor component...
US-7,230,290 Digital magnetic storage cell device
A digital magnetic memory cell device for read and/or write operation includes a soft-magnetic read and/or write layer system and at least one hard-magnetic...
US-7,230,241 Method for matching two measurement methods for measuring structure widths on a substrate
The invention relates to a method for matching a first measurement method for measuring structure widths of trapezoidally tapering structures on a substrate...
US-7,229,928 Method for processing a layered stack in the production of a semiconductor device
A resist layer is deposited a resist layer on a first layer of a layered stack. The stack also includes a second layer below the first layer. The resist layer is...
US-7,229,918 Nitrogen rich barrier layers and methods of fabrication thereof
Methods of forming barrier layers and structures thereof are disclosed. A nitrogen rich region is formed at a top surface of a barrier layer by exposing the...
US-7,229,857 Method for producing a protection for chip edges and system for the protection of chip edges
The invention relates to a method for producing a protection for the chip edges of electronic components that are not provided with a housing, according to which...
US-7,229,851 Semiconductor chip stack
A the semiconductor chip stack in which an intermediate space between semiconductor chips is filled at least along one edge of the upper face of a top chip by a...
US-7,229,723 Method for forming an opening in a light-absorbing layer on a mask
An opening is formed in a light-absorbing layer on a mask by applying a second resist above a first resist on the layer. A first exposure step with subsequent...
US-7,228,569 Programmable unit
A programmable unit is described. The programmable unit has a memory device and a read protection device by which it is possible to prevent data from being read...
US-7,228,477 Apparatus and method for testing circuit units to be tested
Apparatus and Method for Testing Circuit Units To Be Tested. According to one aspect, a test apparatus for testing circuit units to be tested, includes a nominal...
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