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Semiconductor component having a pn junction and a passivation layer
applied on a surface
The invention relates to a semiconductor component having a semiconductor body (100) and at least one pn junction present in the semiconductor body (100) and an...
To provide a circuit board with improved electrical features with respect to a synchronization of signals, a circuit board comprises a dielectric substrate and a...
Formation of active area using semiconductor growth process without STI
A semiconductor device can be formed without use of an STI process. An insulating layer is formed over a semiconductor body. Portions of the insulating layer are...
Power transistor arrangement and method for fabricating it
When fabricating trench power transistor arrangements (1) with active cell array trenches (5) and passive connecting trenches (6), the cell array trenches (5)...
Charge-trapping memory device and method for production
A thin SiGe layer is provided as an additional lower gate electrode layer and is arranged between a thin gate oxide and a gate electrode layer, preferably of...
Method for determining the relative positional accuracy of two structure
elements on a wafer
A measurement mark (3) for determining the relative positional accuracy of a progressive projection onto a wafer (5), the projection being performed with two...
Test reading apparatus for memories
Test reading apparatus having a memory device having individual memory cells, a buffer device, which is connected to the memory device, and which stores data...
Processor system, especially a processor system for communications devices
The invention relates to a processor system which is configured as a communications controller and which comprises a central processor unit (1) for executing...
Lithography method and system with correction of overlay offset errors
caused by wafer processing
A method of controlling lithographic overlay offsets in the manufacture of semiconductor devices from wafers, comprising the steps of forming a lithographic...
Method and circuit arrangement for controlling a subscriber line interface
The invention provides a method for controlling a subscriber line interface circuit, which is connected to at least one data line and to at least one subscriber...
Receiver having an integrated clock phase detector
Receiver is provided having an integrated clock phase detector for the detection of the clock phase deviation between desired sampling instants and the sampling...
Circuit arrangement for recovering clock and data from a received signal
A circuit arrangement to recover clock and data from a received signal comprises an electronic commutator for sampling the received signal in such a way that...
High-speed interface circuit for semiconductor memory chips and memory
system including semiconductor memory chips
A high-speed interface circuit is implemented in a semiconductor memory chip including a memory core, a first interface circuit section, and a second interface...
Semi-conductor component, as well as a process for the in-or output of
The invention relates to a semi-conductor component, and a process for the in- and/or output of test data and/or semi-conductor component operating control data...
Method for testing an integrated semiconductor memory
A method for testing an integrated semiconductor memory provides for disturbing memory cells arranged along a first word line by a disturbance signal on an...
Electronic memory apparatus, and method for deactivating redundant bit
lines or word lines
Electronic memory apparatus, and method for deactivating redundant bit lines or word linesAn electronic memory apparatus (100) having a memory cell array (101),...
DQS for data from a memory array
A memory comprises a first circuit, a second circuit, and a latch. The first circuit is configured to provide a first signal indicating an earliest time valid...
Method for programming multi-bit charge-trapping memory cell arrays
A programming voltage is applied to source and drain in order to generate hot-hole injection at one end of the channel of a memory cell. The undesired...
Semiconductor memory having charge trapping memory cells and fabrication
In the case of this semiconductor memory having NROM cells, the channel regions of the memory transistors in each case run transversely with respect to the...
Switchable operational amplifier circuit
An amplifier circuit in particular configured as an operational transconductance amplifier has signal paths switched in parallel to the individual transversal...
Power amplifier arrangement, and a method for amplification of a signal
A power amplifier arrangement is disclosed which has two or more amplifiers connected in parallel. The amplifiers can be switched on and off independently of one...
Circuit and method for switching an electrical load on after a delay
A circuit (S1) for switching on an electrical load which can be connected downstream from the circuit comprises a first electronic switching means (T1) in a...
Process and device for outputting a digital signal
To output a digital signal in particular according to the LVDS (low voltage differential signalling) standard, a driver stage is supplied with a constant current...
Electronic component and electronic configuration
An electronic component includes a substrate with outer contact areas comprising copper. Lead-free solder bumps are disposed on the outer contact areas of the...
Configurable gate array cell with extended poly gate terminal
A configurable gate array cell contains at least two doping zones of a different conduction type and a poly gate terminal. In a plan view representation of the...
Method for fabricating contact-making connections
The invention provides a method for fabricating contact-making connections, having the steps of: a) providing a substrate (101) with electronic circuit units...
Transistor structure, memory cell, DRAM, and method for fabricating a
transistor structure in a semiconductor...
Transistor structures, with one source/drain region connected to a charge storage device to be insulated includes an asymmetric gate conductor structure. At a...
Process for producing a nanoelement arrangement, and nanoelement
A process for producing a nanoelement arrangement and to a nanoelement arrangement. A first nanoelement is at least partially covered with catalyst material for...
Process for fabrication of a ferrocapacitor
A process for fabricating a ferrocapacitor comprises etching a layer of amorphous PZT formed over a layer having a low concentration of nucleation centres for...
Method for producing a mask set for lithography including at least one
mask and methods for imaging structures...
A method for producing a mask set for lithography including at least one mask, has a predetermined layout of structures which are provided for imaging into a...
Modular system of optoelectronic components, and optoelectronic component
for use in such a system
In a modular system of optoelectronic components each component has a standardized housing. The standard housing has a device for the mechanical connection to at...
Method for comparing the address of a memory access with an already known
address of a faulty memory cell
A comparison method compares the address of a memory cell with a known address of a faulty memory cell in a semiconductor memory module. The module is subdivided...
Data processing apparatus and method for operating a data processing
module for secure power saving
A data processing apparatus comprises a data processing module, which can be operated in a first operating mode with a normal power consumption and a second...
Integrated memory having redundant units of memory cells and method for
testing an integrated memory
An integrated memory has individually addressable normal and redundant units of memory cells. A memory unit is used to store, in a normal mode, an address for...
Method for synchronizing a cache memory with a main memory
Method for synchronizing a cache memory with a main memory, the cache memory provided to buffer-store data between a processor and the main memory, and memory...
Method and apparatus for synthetic widening of the bandwidth of voice
The invention provides a method and an apparatus for synthetic widening of the bandwidth of voice signals. This is done by providing a narrowband voice signal at...
Memory device, memory controller and memory system having bidirectional
One embodiment of the present invention provides to a memory device adapted to receive data according to a write clock signal and to output data according to a...
Integrated semiconductor memory comprising at least one word line and
comprising a multiplicity of memory cells
An integrated semiconductor memory includes at least one word line and a number of memory cells. Each memory cell has a selection transistor coupled to the word...
Differental current source for generating DRAM refresh signal
A circuit for generating a refresh signal for a memory cell of a semiconductor memory includes a capacitor and a differential current source for providing a...
Circuit for setting one of a plurality of organization forms of an
integrated circuit and method for operating it
A circuit for setting one of a plurality of organization forms of an integrated circuit includes a detector circuit connected to an external connection of the...
Direct frequency modulation system having an IQ mixer in the phase locked
A transmission arrangement includes a step-up frequency mixer that converts a modulation signal to a transmission frequency. The step-up frequency mixer is...
Arrangement with a capacitor which can be connected into a circuit and
disconnected therefrom and associated method
An arrangement and a method for connecting a capacitor into a circuit and disconnecting it therefrom are disclosed. The capacitor includes two capacitor...
Phase locked loop and method for trimming a loop filter
The invention includes a phase locked loop which has a voltage-controlled oscillator, a phase comparator and a charge pump. The charge pump is coupled to a...
Method for switching driving of a semiconductor switching element
A method of driving a semiconductor switching element includes applying a drive signal configured to switch the semiconductor element such that a change in the...
Clock synchronization circuit
A clock synchronization circuit for synchronizing a first clock signal and a second clock signal for data transfer from a first function block, which is clocked...
Test device for wafer testing digital semiconductor circuits
The invention relates to a test device for testing digital semiconductor circuits at wafer level having a probe card which sends/receives digital test signals...
Wafer lifting device
The invention, which relates to a wafer lifting device having a lifting platform arranged under a wafer receptacle, which lifting platform can be moved in the...
Method for driving pulse-width-controlled inductive loads, and a drive
circuit for this purpose
When a switch (20) that is in series with the inductive load (10) is turned on, the rise behavior of the current (I) is first of all detected until a nominal...
Arrangement for reducing stress in substrate-based chip packages
An arrangement reduces stress in substrate-based chip packages, in particular of Ball Grid Arrays (BGA) with rear-side and/or edge protection. The chip is firmly...
MRAM storage device
A MRAM storage device comprises a substrate, on/above of which a plurality of word lines, a plurality of bit lines, a plurality of memory cells, and a plurality...