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Patent # Description
US-7,206,712 Test apparatus and test method for mixed-signal semiconductor components
A semiconductor component is tested by providing a tester, a loadboard and an evaluation apparatus. The semiconductor component is operated using a test...
US-7,206,248 Voltage booster device for semi-conductor components
A semi-conductor component (1), in particular a memory component, with at least one voltage booster, which makes available an appropriate boosted voltage (VPP,...
US-7,206,245 Methods and apparatus for implementing standby mode in a random access memory
A memory device includes: a generator system having a number of generators that supply voltage or current to the memory device, a controller that supplies to the...
US-7,206,238 Integrated semiconductor memory comprising at least one word line and method
A semiconductor memory and a test method for testing whether word line segments (12) are floating after an activation operation or a deactivation operation is...
US-7,205,849 Phase locked loop including an integrator-free loop filter
A phase locked loop PLL having a forward path and a feedback path is disclosed. A phase detector drives an oscillator in the forward path of the phase locked...
US-7,205,845 Amplifier circuit for converting the current signal from an optical receiving element into a voltage signal
An amplifier circuit for converting the current signal from an optical receiving element into a voltage signal. The amplifier circuit includes a transimpedance...
US-7,205,829 Clocked standby mode with maximum clock frequency
A method and apparatus for controlling a voltage generator of a memory device are provided. In one embodiment, a first clock signal and a second clock signal are...
US-7,205,639 Semiconductor devices with rotated substrates and methods of manufacture thereof
Integrated circuits are oriented on a substrate at an angle that is rotated between 0 to 45 degrees from a direction parallel or perpendicular to a preferred...
US-7,205,596 Adiabatic rotational switching memory element including a ferromagnetic decoupling layer
A magnetoresistive memory element includes a stacked structure with a ferromagnetic reference region including a fixed magnetization; a ferromagnetic free region...
US-7,205,581 Thyristor structure and overvoltage protection configuration having the thyristor structure
A thyristor structure having a first terminal, formed as a first region with a first conductivity type, is provided. A second region of a second conductivity...
US-7,205,567 Semiconductor product having a semiconductor substrate and a test structure and method
A semiconductor product having a test structure, in which a contact connection short-circuits that source/drain region of a transistor which is connected to an...
US-7,205,243 Process for producing a mask on a substrate
To produce a mask, a first mask layer (40) is applied to the substrate (10). During or after the deposition of the first mask layer (40), the latter is exposed...
US-7,205,195 Method for fabricating NROM memory cells with trench transistors
An electrically conductive bit line layer is applied and patterned into portions arranged parallel to one another before the trench is etched into the...
US-7,204,068 Packaging system with a tool for enclosing electronic components and method of populating a carrier tape
The invention relates to a packaging system having a tool for inserting electronic components into a carrier tape, which has passage openings. The tool has a...
US-7,203,883 Integrated circuit
An integrated semiconductor memory, which can be operated in a normal operating state and a test operating state, includes a current pulse circuit with an input...
US-7,203,859 Variable clock configuration for switched op-amp circuits
A clock configuration for driving switched op-amp circuits operated in opposite phases is presented in which a common off-phase of variable length is inserted...
US-7,203,618 Method and device for adjusting a determination rule of an angle sensor
A method for adjusting a determination rule for an error compensation of an angle sensor is designed to detect a first component of a direction along a first...
US-7,203,466 Transmitting and receiving unit
A transmitting and receiving unit includes a receiving branch and a transmitting branch that are in each case constructed for conducting complex signals, with a...
US-7,203,127 Apparatus and method for dynamically controlling data transfer in memory device
Methods and apparatus for operating a secondary sense amplifier according to different timings. Embodiments of the invention generally provide a secondary sense...
US-7,203,123 Integrated DRAM memory device
An integrated memory device including a number of memory blocks including memory cells wherein the memory cells are arranged in a matrix of wordlines and...
US-7,203,106 Integrated semiconductor memory with redundant memory cells
An integrated semiconductor memory has regular row and column lines, which can be replaced with redundant row and column lines in the event of a fault. Following...
US-7,203,102 Semiconductor memory having tri-state driver device
A semiconductor memory having at least one memory cell adapted to store a data value, and adapted to be connected to a data line through a switch device...
US-7,203,096 Method and apparatus for sensing a state of a memory cell
A cell arrangement comprising a memory cell arranged in parallel to a first capacitor is charged to a first voltage potential. A second capacitor is charged to a...
US-7,202,718 Error-compensated charge pump circuit, and method for producing an error-compensated output current from a...
A charge pump circuit has a charge pump having at least two switched current sources arranged in series. The difference between the currents produced in the two...
US-7,202,547 Capacitor with a dielectric including a self-organized monolayer of an organic compound
A capacitor is formed that includes a self-organized monolayer of an organic compound between two electrodes.
US-7,202,545 Memory module and method for operating a memory module
A memory module has an electronic printed circuit board and a plurality of semiconductor memory chips. A series circuit of the semiconductor memory chips is...
US-7,202,535 Manufacturing method for an integrated semiconductor structure and corresponding integrated semiconductor structure
The present invention provides a manufacturing method for an integrated semiconductor structure and a corresponding integrated semiconductor structure. The...
US-7,202,529 Field effect transistor
A field effect transistor includes a substrate having a doping of a first conductivity type, a drain area in the substrate having a doping of a second...
US-7,202,527 MOS transistor and ESD protective device each having a settable voltage ratio of the lateral breakdown voltage...
A MOS transistor includes a drain zone, a source zone, and a gate electrode. Doping atoms of the first conductivity type are implanted in the region of the drain...
US-7,202,107 Method for producing a semiconductor component with a plastic housing and carrier plate for performing the method
A process for producing a semiconductor component having a plastic housing in which at least one semiconductor chip is arranged includes providing a ...
US-7,201,634 Polishing methods and apparatus
Apparatus for and methods of chemical mechanical polishing (CMP) of semiconductor wafers are disclosed. A preferred embodiment comprises an apparatus for...
US-7,200,629 Apparatus and method for Fast Hadamard Transforms
A Fast Hadamard Transform generator serially performs a Fast Hadamard Transform of a sampled signal from a first channel. The Fast Hadamard Transform generator...
US-7,200,042 Method and circuit arrangement for reading from a flash/EEPROM memory cell
The invention is based on a method for reading out the content of a flash/EEPROM memory cell, in which a read current flowing via a read-out path with a memory...
US-7,200,033 MRAM with coil for creating offset field
An MRAM memory chip includes a plurality of magnetoresistive memory cells each including a magnetic tunnel junction having first (fixed) and second (free)...
US-7,200,032 MRAM with vertical storage element and field sensor
A magnetic memory element comprising a magnetic storage element having at least one magnetic layer made of a magnetic material and being vertically oriented...
US-7,200,021 Stacked DRAM memory chip for a dual inline memory module (DIMM)
A stacked DRAM memory chip for a Dual In Line Memory Module (DIMM) is disclosed. According to one aspect, the DRAM memory chip comprises at least four stacked...
US-7,199,741 Method for digital/analog conversion and corresponding digital/analog converter device
A method and a device for digital/analog conversion are proposed, whereby for improved use of a "dynamic element matching" algorithm, in particular a "data...
US-7,199,684 Filter circuit with a filter stage and balun on a single substrate
A filter circuit comprises a balanced port, an unbalanced port and a substrate. A series circuit of a filter stage and a balun is disposed between the balanced...
US-7,199,683 BAW resonator
A BAW resonator includes a resonator region having a piezo-electric layer between two excitation electrodes, wherein an acoustic standing wave forms when...
US-7,199,672 Phase-locked loop with a pulse generator, and method for operating the phase-locked loop
The phase-locked loop has a pulse generator has a phase detector which is intended to compare a reference signal with an oscillator signal, and a detector output...
US-7,199,667 Integrated power amplifier arrangement
An integrated power amplifier arrangement with multistage construction is provided, in which a matching filter with integrated capacitance and inductance for...
US-7,199,629 Circuit having delay locked loop for correcting off chip driver duty distortion
A circuit comprises an off chip driver and a delay locked loop. The delay locked loop is configured to receive a clock signal and provide a first signal for...
US-7,199,625 Delay locked loop structure providing first and second locked clock signals
A delay locked loop including a first circuit and a second circuit. The first circuit is configured to receive a clock signal having a frequency and to lock onto...
US-7,199,618 Logic circuit arrangement
A logic circuit arrangement including at least two data signal inputs, at which at least two data signals are provided, a first signal path coupled to the data...
US-7,199,607 Pin multiplexing
There is provided a semiconductor device for multiplexing across a plurality of shared Input/Output (I/O) pins. The semiconductor device comprises a first core...
US-7,199,589 Method for controlling a switching converter and control device for a switching converter
A method and a device is provided for controlling a switching converter comprising a high side switch and a low side switch. The method comprises testing the...
US-7,199,448 Integrated circuit configuration comprising a sheet-like substrate
An integrated circuit is formed on a non-planar substrate. The integrated circuit is formed over a plurality of layers. Chemical or physical changes in the...
US-7,199,414 Stress-reduced layer system for use in storage capacitors
The stress-reduced layer system has at least one first layer of polycrystalline or single-crystal semiconductor material, which adjoins a microcrystalline or...
US-7,199,403 Semiconductor arrangement having a MOSFET structure and a zener device
The invention relates to a semiconductor arrangement having a MOSFET structure and an active zener function. A n.sup.+-doped zone and a p.sup.+-doped zone are...
US-7,199,062 Method for forming a resist film on a substrate having non-uniform topography
A preferred embodiment of the invention provides a method of spin coating a liquid, such as a resist, onto a surface of a substrate. An embodiment of the...
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