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Patent # Description
US-7,190,605 Semiconductor memory and method for operating a semiconductor memory comprising a plurality of memory cells
A method for operating a semiconductor memory (M) including a plurality of memory cells (MC), wherein the memory cells (MC) are arranged adjacent to one another,...
US-7,190,220 Circuit for providing a base operating voltage for a bipolar transistor and amplifier circuit
A circuit for providing a base operating voltage for a bipolar transistor includes a U.sub.BE multiplier providing, in response to a working-point control...
US-7,190,077 Semiconductor structure integrated under a pad
An integrated semiconductor structure has a substrate, a semiconductor element located on the substrate, a pad metal, metal layers located between the pad metal...
US-7,190,059 Electronic component with a stack of semiconductor chips and a method for producing the electronic component
The invention relates to a method for producing an electronic component, a stack of semiconductor chips, and an electronic component including a stack of...
US-7,190,038 Micromechanical sensors and methods of manufacturing same
A micromechanical sensor and, in particular, a silicon microphone, includes a movable membrane and a counter element in which perforation openings are formed,...
US-7,190,022 One transistor flash memory cell
An integrated circuit has a high voltage area, a logic area and a memory array for forming a system on a chip that includes linear, logic and memory devices. The...
US-7,189,988 Molecular electronics arrangement and method for producing a molecular electronics arrangement
The invention relates to a molecular electronics arrangement comprising a substrate, at least one first strip conductor having a surface and being arranged in or...
US-7,189,617 Manufacturing method for a recessed channel array transistor and corresponding recessed channel array transistor
The present invention relates to a manufacturing method for a recessed channel array transistor and a corresponding recessed channel array transistor. In one...
US-7,189,614 Method for fabricating a trench structure which is electrically connected to a substrate on one side via a...
A method for fabricating a trench structure, in particular a trench capacitor with an insulation collar, which is electrically connected to a substrate on one...
US-7,189,009 Micro-optical module with housing and method for producing the same
A micro-optical module includes a housing, at least one optoelectronic component, and an optoelectronic unit assigned thereto. The housing is partly embodied as...
US-7,188,321 Generation of metal holes by via mutation
A reduction in the intersection of vias on the last layer ("VL") and holes in the last thin metal layer ("MLHOLE") can be achieved without degrading product...
US-7,188,291 Circuit and method for testing a circuit having memory array and addressing and control unit
A circuit configuration for testing a circuit using a test device for providing a test mode, where test procedures are performed sequentially. The test...
US-7,188,204 Memory unit and branched command/address bus architecture between a memory register and a plurality of memory units
A branched command/address bus architecture between a memory register and a plurality of memory units includes a main bus connected to the memory register. A...
US-7,188,159 Efficient software download to configurable communication device
An efficient software download to a configurable communication device is disclosed herein. The method of efficiently downloading software begins with a step of...
US-7,187,612 Memory having power-up circuit
A memory includes a power-up circuit configured to increase a first voltage to a first value with a second voltage tied to ground, reduce the first voltage from...
US-7,187,602 Reducing memory failures in integrated circuits
Memory reliability is improved by using redundancy to repair errors detected by ECC. In one embodiment, redundancy repairs errors which cannot be corrected by...
US-7,187,599 Integrated circuit chip having a first delay circuit trimmed via a second delay circuit
An integrated circuit chip including a first delay circuit and a second delay circuit. The first delay circuit has a first delay circuit topology configured to...
US-7,187,589 Non-volatile semiconductor memory and method for writing data into a non-volatile semiconductor memory
Data is written into a non-volatile semiconductor memory using one of at least four steps. A first step is executed if the final states of both the first bit...
US-7,187,576 Read out scheme for several bits in a single MRAM soft layer
A magnetic tunnel junction (MTJ) device is configured to store at least two bits of data in a single cell utilizing the variable resistance characteristic of a...
US-7,187,246 Oscillator circuit
In the case of a voltage-controlled LC oscillator (4), the effects of supply voltage fluctuations are reduced according to the invention, due to the fact that a...
US-7,187,238 Circuit for adjusting the operating point of multiple gate field effect transistors
An amplifier circuit includes a first multiple gate field-effect transistor having a source terminal, a drain terminal, at least one signal gate terminal for...
US-7,187,221 Digital duty cycle corrector
A method for adjusting the relative phases of two signals includes receiving first and second signals, which may, for example, be derived from a differential...
US-7,187,218 Reset generator circuit for generating a reset signal
A reset generator circuit has an oscillator circuit and a delay circuit having a clock signal input, which is connected to an output of the oscillator circuit....
US-7,187,196 Low rise/fall skewed input buffer compensating process variation
Buffer circuits and techniques that reduce skew between rising and falling times of output data as process conditions vary are provided. One or more ...
US-7,187,058 Semiconductor component having a pn junction and a passivation layer applied on a surface
The invention relates to a semiconductor component having a semiconductor body (100) and at least one pn junction present in the semiconductor body (100) and an...
US-7,186,922 Circuit board
To provide a circuit board with improved electrical features with respect to a synchronization of signals, a circuit board comprises a dielectric substrate and a...
US-7,186,622 Formation of active area using semiconductor growth process without STI integration
A semiconductor device can be formed without use of an STI process. An insulating layer is formed over a semiconductor body. Portions of the insulating layer are...
US-7,186,618 Power transistor arrangement and method for fabricating it
When fabricating trench power transistor arrangements (1) with active cell array trenches (5) and passive connecting trenches (6), the cell array trenches (5)...
US-7,186,607 Charge-trapping memory device and method for production
A thin SiGe layer is provided as an additional lower gate electrode layer and is arranged between a thin gate oxide and a gate electrode layer, preferably of...
US-7,186,484 Method for determining the relative positional accuracy of two structure elements on a wafer
A measurement mark (3) for determining the relative positional accuracy of a progressive projection onto a wafer (5), the projection being performed with two...
US-7,185,245 Test reading apparatus for memories
Test reading apparatus having a memory device having individual memory cells, a buffer device, which is connected to the memory device, and which stores data...
US-7,185,184 Processor system, especially a processor system for communications devices
The invention relates to a processor system which is configured as a communications controller and which comprises a central processor unit (1) for executing...
US-7,184,853 Lithography method and system with correction of overlay offset errors caused by wafer processing
A method of controlling lithographic overlay offsets in the manufacture of semiconductor devices from wafers, comprising the steps of forming a lithographic...
US-7,184,543 Method and circuit arrangement for controlling a subscriber line interface circuit
The invention provides a method for controlling a subscriber line interface circuit, which is connected to at least one data line and to at least one subscriber...
US-7,184,504 Receiver having an integrated clock phase detector
Receiver is provided having an integrated clock phase detector for the detection of the clock phase deviation between desired sampling instants and the sampling...
US-7,184,502 Circuit arrangement for recovering clock and data from a received signal
A circuit arrangement to recover clock and data from a received signal comprises an electronic commutator for sampling the received signal in such a way that...
US-7,184,360 High-speed interface circuit for semiconductor memory chips and memory system including semiconductor memory chips
A high-speed interface circuit is implemented in a semiconductor memory chip including a memory core, a first interface circuit section, and a second interface...
US-7,184,339 Semi-conductor component, as well as a process for the in-or output of test data
The invention relates to a semi-conductor component, and a process for the in- and/or output of test data and/or semi-conductor component operating control data...
US-7,184,337 Method for testing an integrated semiconductor memory
A method for testing an integrated semiconductor memory provides for disturbing memory cells arranged along a first word line by a disturbance signal on an...
US-7,184,335 Electronic memory apparatus, and method for deactivating redundant bit lines or word lines
Electronic memory apparatus, and method for deactivating redundant bit lines or word linesAn electronic memory apparatus (100) having a memory cell array (101),...
US-7,184,328 DQS for data from a memory array
A memory comprises a first circuit, a second circuit, and a latch. The first circuit is configured to provide a first signal indicating an earliest time valid...
US-7,184,317 Method for programming multi-bit charge-trapping memory cell arrays
A programming voltage is applied to source and drain in order to generate hot-hole injection at one end of the channel of a memory cell. The undesired...
US-7,184,291 Semiconductor memory having charge trapping memory cells and fabrication method
In the case of this semiconductor memory having NROM cells, the channel regions of the memory transistors in each case run transversely with respect to the...
US-7,183,850 Switchable operational amplifier circuit
An amplifier circuit in particular configured as an operational transconductance amplifier has signal paths switched in parallel to the individual transversal...
US-7,183,841 Power amplifier arrangement, and a method for amplification of a signal
A power amplifier arrangement is disclosed which has two or more amplifiers connected in parallel. The amplifiers can be switched on and off independently of one...
US-7,183,816 Circuit and method for switching an electrical load on after a delay
A circuit (S1) for switching on an electrical load which can be connected downstream from the circuit comprises a first electronic switching means (T1) in a...
US-7,183,804 Process and device for outputting a digital signal
To output a digital signal in particular according to the LVDS (low voltage differential signalling) standard, a driver stage is supplied with a constant current...
US-7,183,652 Electronic component and electronic configuration
An electronic component includes a substrate with outer contact areas comprising copper. Lead-free solder bumps are disposed on the outer contact areas of the...
US-7,183,594 Configurable gate array cell with extended poly gate terminal
A configurable gate array cell contains at least two doping zones of a different conduction type and a poly gate terminal. In a plan view representation of the...
US-7,183,188 Method for fabricating contact-making connections
The invention provides a method for fabricating contact-making connections, having the steps of: a) providing a substrate (101) with electronic circuit units...
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