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Capacitor with a dielectric including a self-organized monolayer of an
A capacitor is formed that includes a self-organized monolayer of an organic compound between two electrodes.
Memory module and method for operating a memory module
A memory module has an electronic printed circuit board and a plurality of semiconductor memory chips. A series circuit of the semiconductor memory chips is...
Manufacturing method for an integrated semiconductor structure and
corresponding integrated semiconductor structure
The present invention provides a manufacturing method for an integrated semiconductor structure and a corresponding integrated semiconductor structure. The...
Field effect transistor
A field effect transistor includes a substrate having a doping of a first conductivity type, a drain area in the substrate having a doping of a second...
MOS transistor and ESD protective device each having a settable voltage
ratio of the lateral breakdown voltage...
A MOS transistor includes a drain zone, a source zone, and a gate electrode. Doping atoms of the first conductivity type are implanted in the region of the drain...
Method for producing a semiconductor component with a plastic housing and
carrier plate for performing the method
A process for producing a semiconductor component having a plastic housing in which at least one semiconductor chip is arranged includes providing a ...
Polishing methods and apparatus
Apparatus for and methods of chemical mechanical polishing (CMP) of semiconductor wafers are disclosed. A preferred embodiment comprises an apparatus for...
Apparatus and method for Fast Hadamard Transforms
A Fast Hadamard Transform generator serially performs a Fast Hadamard Transform of a sampled signal from a first channel. The Fast Hadamard Transform generator...
Method and circuit arrangement for reading from a flash/EEPROM memory cell
The invention is based on a method for reading out the content of a flash/EEPROM memory cell, in which a read current flowing via a read-out path with a memory...
MRAM with coil for creating offset field
An MRAM memory chip includes a plurality of magnetoresistive memory cells each including a magnetic tunnel junction having first (fixed) and second (free)...
MRAM with vertical storage element and field sensor
A magnetic memory element comprising a magnetic storage element having at least one magnetic layer made of a magnetic material and being vertically oriented...
Stacked DRAM memory chip for a dual inline memory module (DIMM)
A stacked DRAM memory chip for a Dual In Line Memory Module (DIMM) is disclosed. According to one aspect, the DRAM memory chip comprises at least four stacked...
Method for digital/analog conversion and corresponding digital/analog
A method and a device for digital/analog conversion are proposed, whereby for improved use of a "dynamic element matching" algorithm, in particular a "data...
Filter circuit with a filter stage and balun on a single substrate
A filter circuit comprises a balanced port, an unbalanced port and a substrate. A series circuit of a filter stage and a balun is disposed between the balanced...
A BAW resonator includes a resonator region having a piezo-electric layer between two excitation electrodes, wherein an acoustic standing wave forms when...
Phase-locked loop with a pulse generator, and method for operating the
The phase-locked loop has a pulse generator has a phase detector which is intended to compare a reference signal with an oscillator signal, and a detector output...
Integrated power amplifier arrangement
An integrated power amplifier arrangement with multistage construction is provided, in which a matching filter with integrated capacitance and inductance for...
Circuit having delay locked loop for correcting off chip driver duty
A circuit comprises an off chip driver and a delay locked loop. The delay locked loop is configured to receive a clock signal and provide a first signal for...
Delay locked loop structure providing first and second locked clock
A delay locked loop including a first circuit and a second circuit. The first circuit is configured to receive a clock signal having a frequency and to lock onto...
Logic circuit arrangement
A logic circuit arrangement including at least two data signal inputs, at which at least two data signals are provided, a first signal path coupled to the data...
There is provided a semiconductor device for multiplexing across a plurality of shared Input/Output (I/O) pins. The semiconductor device comprises a first core...
Method for controlling a switching converter and control device for a
A method and a device is provided for controlling a switching converter comprising a high side switch and a low side switch. The method comprises testing the...
Integrated circuit configuration comprising a sheet-like substrate
An integrated circuit is formed on a non-planar substrate. The integrated circuit is formed over a plurality of layers. Chemical or physical changes in the...
Stress-reduced layer system for use in storage capacitors
The stress-reduced layer system has at least one first layer of polycrystalline or single-crystal semiconductor material, which adjoins a microcrystalline or...
Semiconductor arrangement having a MOSFET structure and a zener device
The invention relates to a semiconductor arrangement having a MOSFET structure and an active zener function. A n.sup.+-doped zone and a p.sup.+-doped zone are...
Method for forming a resist film on a substrate having non-uniform
A preferred embodiment of the invention provides a method of spin coating a liquid, such as a resist, onto a surface of a substrate. An embodiment of the...
Method for patterning dielectric layers on semiconductor substrates
The invention relates to a process for patterning dielectric layers. A photoresist layer is applied to the dielectric layer and patterned. Then, the pattern...
Process for fabrication of a ferroelectric capacitor
A process for the fabrication of a ferroelectric capacitor comprising depositing a layer of Ti 5 over an insulating layer 3 of Al.sub.2O.sub.3, and oxidising the...
Method for manufacturing a stack arrangement of a memory module
A method of stacking semiconductor chips includes providing four semiconductor chips that each include a top surface with central bond pads. Each of the bond...
Process for fabrication of a ferrocapacitor
In a process for fabricating a ferrocapacitor comprising providing ferroelectric PZT elements over an Al.sub.2O.sub.3 layer, the Al.sub.2O.sub.3 layer is covered...
Arrangement for determining a temperature loading of an integrated circuit
In an arrangement for determining a temperature loading during a soldering process, a semiconductor chip (1) comprises at least one contact (2) to be soldered or...
Method for testing an integrated semiconductor memory with a shortened
An integrated semiconductor memory operates in synchronization with a clock signal in a normal operating state and is switched from the normal operating state to...
Test circuit and method for testing an integrated memory circuit
A test circuit for testing a memory circuit has a data input line for providing test data and a comparator unit. The comparator unit is connected to the data...
Circuit, system and method for encoding data to be stored on a
non-volatile memory array
The present invention is a method, circuit and system for storing bits on a Non-Volatile Memory ("NVM") array. According to some embodiments of the present...
Method and arrangement for fast frequency searching in broadband mobile
In the method according to the invention for searching for the carrier frequency f of a mobile radio transmitter in a mobile radio receiver, two or more values...
Sensing current recycling method during self-refresh
A bit line sensing scheme is provided for a semiconductor memory device that significantly reduces current drain during a self-refresh mode. After bit line...
Random access memory having voltage provided out of boosted supply voltage
A random access memory including an array of single transistor memory cells and a voltage source. The voltage source is configured to receive a boosted supply...
Integrated circuit for stabilizing a voltage
An integrated circuit includes an input terminal (IN) for application of a supply voltage (Vext) and an output terminal (A) for generation of an output voltage...
Integrated clock supply chip for a memory module, memory module comprising
the integrated clock supply chip,...
An integrated chip has a clock signal input (1.1) for application of a first clock signal (clk1) and a clock signal output (1.2 1.5). Moreover, it has a phase...
An integrated circuit includes a circuit component, a first control circuit and a switchable resistance network. An input voltage is fed to the circuit component...
Hall switch arrangement
The Hall switch arrangement comprises a plurality of Hall switch elements connected in series with a first Hall switch element, wherein the first Hall switch...
ESD protection apparatus for an electrical device
An ESD protection apparatus for an electrical device with a circuit structure having an internal terminal, which is connected to an external terminal of the...
Semiconductor package with heat spreader
A semiconductor package with heat spreader is disclosed. In one embodiment, the semiconductor package comprises a device carrier having a plurality of contact...
Method for production of deep p regions in silicon, and semiconductor
components produced using the method
The invention relates to a method for production of deep p regions in silicon, with the method having the following step: bombardment of an n substrate section,...
Method for the production of a memory cell, memory cell and memory cell
Memory cell having an auxiliary substrate, on which a first gate insulating layer is formed, a floating gate formed on the first gate insulating layer, an...
Method for fabricating a trench capacitor with an insulation collar and
corresponding trench capacitor
The present invention provides a method for fabricating a trench capacitor with an insulation collar in a substrate, which is electrically connected to the...
Configuration for in-circuit emulation of a program-controlled unit
A configuration contains a test unit that, during emulation, replaces a program-controlled unit that is used in normal operation of the system containing the...
Capacitive biometric sensor
In a capacitive biometric sensor, in particular, a fingerprint sensor, to determine the maximum contrast that can actually be achieved in that application in the...
Method for determining a reference clock phase from band-limited digital
The invention provides a method for recovering a digital datastream, in which a reference clock phase is recovered from the digital datastream, the digital...
Selective bank refresh
A method of refreshing several memory banks of a memory device that receives command signals from a memory controller. The method includes monitoring command...