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Patent # Description
US-7,212,432 Resistive memory cell random access memory device and method of fabrication
A resistive memory cell random access memory device and method for fabrication. In one embodiment, the invention relates to a resistive memory cell random access...
US-7,212,038 Line driver for transmitting data
A line driver (3) for transmitting data with high bit rates, in particular for wire-bound data transmission in the full-duplex process, comprises a differential...
US-7,212,019 Probe needle for testing semiconductor chips and method for producing said probe needle
A probe needle for testing semiconductor chips includes one end that is fixed in a holding element and a free end that includes a contact tip. The probe needle...
US-7,211,909 Monolithic integrated circuit arrangement
A monolithic integrated circuit arrangement containing a substrate, a functional unit formed in and/or on the substrate, and an energy supply unit, which is...
US-7,211,860 Semiconductor component including plural trench transistors with intermediate mesa regions
In the case of the semiconductor component (1) according to the invention, the source regions (S), the body regions (B) and, if appropriate, the body contact...
US-7,211,856 Resistive memory for low-voltage applications
Memory cells having two electrodes and a layer arranged in between and including an active material which contains hexakisbenzylthiobenzene, ...
US-7,211,846 Transistor having compensation zones enabling a low on-resistance and a high reverse voltage
A semiconductor component includes a semiconductor body having a substrate of a first conduction type and a first layer of a second conduction type that is...
US-7,211,520 Method for fabricating a field effect transistor
A method for fabricating a field effect transistor, in which, after the etching of the gate electrode, the removal of the etching mask is omitted since the...
US-7,211,504 Process and arrangement for the selective metallization of 3D structures
A process is provided for the selective metallization of 3D structures, particularly for the selective gold-plating of 3D contact structures on wafers, such as...
US-7,211,472 Method for producing a multichip module and multichip module
A method for producing a multi-chip module having application of at least one contact elevation onto a substrate, application and patterning of a rewiring device...
US-7,211,451 Process for producing a component module
A process for producing a component module comprising a module carrier and a plurality of components with which contact is made on the latter, comprising the...
US-7,211,446 Method of patterning a magnetic tunnel junction stack for a magneto-resistive random access memory
A method of patterning a magnetic tunnel junction (MTJ) stack is provided. According to such method, an MTJ stack is formed having a free layer, a pinned layer...
US-7,211,355 Method for producing phase shifter masks
The invention relates to a method for producing phase shifter masks for 157 nm lithography. A coating has an organic material and is at least partially...
US-7,210,086 Long running test method for a circuit design analysis
The invention relates to a design analysis technique for a test pattern analysis of chips via automatic test equipment (ATE) or a circuit simulation to detect...
US-7,210,064 Program controlled unit and method for debugging programs executed by a program controlled unit
The described program controlled unit has first supply voltage connections for applying a first supply voltage to the program controlled unit and second supply...
US-7,209,819 Drive circuit for a firing cap of a vehicle restraint system
A drive circuit for a firing cap, triggerable by an electric direct current firing pulse, of a vehicle restraint system, has a firing circuit which forms a...
US-7,209,534 Fractional divider system and method
The present invention relates to a fractional divider system for a low-power timer with reduced timing error at wake-up. The fractional divider system includes a...
US-7,209,516 ADSL system with improved data rate
An improved ADSL system with improved data rate is disclosed. In one embodiment, the upstream data bit rate is increased by extending the upstream transmission...
US-7,209,396 Data strobe synchronization for DRAM devices
Methods and apparatus that determine, at a device (e.g., a DRAM device), a phase difference between two externally supplied timing signals such as a clock signal...
US-7,209,004 DB-linear variable gain amplifier (VGA) stage with a high broad band
The invention relates to a VGA stage having a novel circuit configuration for amplifying/attenuating a differential input signal which is transmitted via a...
US-7,208,968 Test system for testing integrated chips and an adapter element for a test system
Test system for testing integrated chips and an adapter element for a test system. One embodiment provides a test system for testing integrated chips in a...
US-7,208,944 Method for determining the angular position of a rotating object and rotary encoder
A method for determining the angular position of a rotating object and rotary encoder is disclosed. In one embodiment, the method includes a method for...
US-7,208,827 Encasing arrangement for a semiconductor component
A semiconductor component package configuration includes a semiconductor chip mounted to a printed circuit board, and a substrate arranged between the...
US-7,208,823 Semiconductor arrangement comprising transistors based on organic semiconductors and non-volatile read-write...
A semiconductor arrangement is disclosed, having transistors based on organic semiconductors and non-volatile read/write memory cells. The invention relates to a...
US-7,208,814 Resistive device and method for its production
A resistive device includes a resistive region of a semiconductor material that includes a first region and a second region, wherein the first region has a...
US-7,208,794 High-density NROM-FINFET
Semiconductor memory having memory cells, each including first and second conductively-doped contact regions and a channel region arranged between the latter,...
US-7,208,782 Reduction of the contact resistance in organic field-effect transistors with palladium contacts by using...
A semiconductor device includes a semiconductor path, the semiconductor path including an organic semiconductor material, a first contact to inject charge...
US-7,208,416 Method of treating a structured surface
The invention provides a simple method of treating a structured surface comprising a higher surface in a first region and a lower surface in the second region. A...
US-7,208,373 Method of forming a memory cell array and a memory cell array
A method of forming a memory cell array comprising a plurality of memory cells, each of the memory cells including a trench capacitor and a transistor is...
US-7,208,370 Method for fabricating a vertical transistor in a trench, and vertical transistor
To fabricate a vertical transistor, a trench is provided, the side wall of which is formed by a semiconductor substrate in single crystal form and the base of...
US-7,208,345 Method of manufacturing a semiconductor device comprising stacked chips and a corresponding semiconductor device
A first reconstituted wafer is formed, followed by a first redistribution layer. In parallel, a second reconstituted wafer is formed. The second reconstituted...
US-7,208,095 Method for fabricating bottom electrodes of stacked capacitor memory cells and method for cleaning and drying a...
Bottom electrodes of stacked capacitor DRAM cells are formed by depositing a metal layer on the side walls of trenches within a hard mask layer, which serves as...
US-7,207,030 Method for improving a simulation model of photolithographic projection
A method is provided for improving a photolithographic simulation model of the photolithographic simulation of a pattern formed on a photomask. Proceeding from a...
US-7,207,016 Method for classifying errors in the layout of a semiconductor circuit
A method for classifying errors in the layout of a semiconductor circuit includes examining the layout of the semiconductor circuit for infringement of...
US-7,206,985 Method and apparatus for calibrating a test system for an integrated semiconductor circuit
A method and an apparatus provides for calibrating a test system for an integrated semiconductor circuit, a pattern generator of the test system generating a...
US-7,206,980 Integrated semiconductor memory
An integrated semiconductor memory includes a memory cell array with at least one memory cell, in which a data value is stored, and an evaluation circuit with a...
US-7,206,978 Error detection in a circuit module
A circuit module has a module board and a plurality of circuit chips that are arranged on the module board. A module main bus having a plurality of lines of the...
US-7,206,926 Programmable unit including program operation unit and associated stopping device
A programmable unit is described having one or more program running units for running a program, with at least one of the program running units having an...
US-7,206,712 Test apparatus and test method for mixed-signal semiconductor components
A semiconductor component is tested by providing a tester, a loadboard and an evaluation apparatus. The semiconductor component is operated using a test...
US-7,206,248 Voltage booster device for semi-conductor components
A semi-conductor component (1), in particular a memory component, with at least one voltage booster, which makes available an appropriate boosted voltage (VPP,...
US-7,206,245 Methods and apparatus for implementing standby mode in a random access memory
A memory device includes: a generator system having a number of generators that supply voltage or current to the memory device, a controller that supplies to the...
US-7,206,238 Integrated semiconductor memory comprising at least one word line and method
A semiconductor memory and a test method for testing whether word line segments (12) are floating after an activation operation or a deactivation operation is...
US-7,205,849 Phase locked loop including an integrator-free loop filter
A phase locked loop PLL having a forward path and a feedback path is disclosed. A phase detector drives an oscillator in the forward path of the phase locked...
US-7,205,845 Amplifier circuit for converting the current signal from an optical receiving element into a voltage signal
An amplifier circuit for converting the current signal from an optical receiving element into a voltage signal. The amplifier circuit includes a transimpedance...
US-7,205,829 Clocked standby mode with maximum clock frequency
A method and apparatus for controlling a voltage generator of a memory device are provided. In one embodiment, a first clock signal and a second clock signal are...
US-7,205,639 Semiconductor devices with rotated substrates and methods of manufacture thereof
Integrated circuits are oriented on a substrate at an angle that is rotated between 0 to 45 degrees from a direction parallel or perpendicular to a preferred...
US-7,205,596 Adiabatic rotational switching memory element including a ferromagnetic decoupling layer
A magnetoresistive memory element includes a stacked structure with a ferromagnetic reference region including a fixed magnetization; a ferromagnetic free region...
US-7,205,581 Thyristor structure and overvoltage protection configuration having the thyristor structure
A thyristor structure having a first terminal, formed as a first region with a first conductivity type, is provided. A second region of a second conductivity...
US-7,205,567 Semiconductor product having a semiconductor substrate and a test structure and method
A semiconductor product having a test structure, in which a contact connection short-circuits that source/drain region of a transistor which is connected to an...
US-7,205,243 Process for producing a mask on a substrate
To produce a mask, a first mask layer (40) is applied to the substrate (10). During or after the deposition of the first mask layer (40), the latter is exposed...
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