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Patent # Description
US-7,277,312 Integrated semiconductor memory with an arrangement of nonvolatile memory cells, and method
In integrated semiconductor memories whose stored information is represented by the magnitude of the ohmic resistance of layer stacks with a respective layer...
US-7,276,978 Phase locked loop comprising a sigma-delta modulator
The invention is directed to a phase locked loop with a .SIGMA..DELTA. modulator. A multimodulus divider in the feedback path of the PLL is actuated by the...
US-7,276,896 Test apparatus and method for testing circuit units to be tested
The invention provides a test apparatus for testing a circuit unit (101) to be tested having a test system (100), a control bus (102) for transferring control...
US-7,276,803 Semiconductor component and method for fabricating
Semiconductor components having a semiconductor body which includes a semiconductor base surface have to be sealed with a molding compound in order to protect...
US-7,276,785 Electronic module, panel having electronic modules which are to be divided up, and process for the production...
The invention relates to an electronic module having electronic components, which are arranged in vertically staggered component layers, which are electrically...
US-7,276,783 Electronic component with a plastic package and method for production
An electronic component with a plastic package and to a method for its production, includes a semiconductor chip. An underside of the plastic package has...
US-7,276,781 Multichip module for LOC mounting and method for producing the multichip module
A multichip module for leads-on-chip mounting is described. The multichip module has a lead-frame, a common, contiguous part of a wafer slice disposed in the...
US-7,276,300 Microelectronic structure having a hydrogen barrier layer
The invention relates to a microelectronic structure which provides improved protection of a hydrogen-sensitive dielectric against hydrogen contamination....
US-7,275,189 Memory module and method for operating a memory module in a data memory system
Memory modules based on DDR-DRAMs are provided with a buffer and error checking module, which integrates an error data memory and a buffer/redriver functionality...
US-7,275,173 Method for measuring and compensating for skews of data transmission lines by compensating for skew by delay...
Method for measuring and compensating skews of data transmission lines connecting at least one data transmission device with a data reception device via a...
US-7,274,867 System and method for determining the temperature of a semiconductor wafer
A system and method for determining the temperature of a semiconductor wafer at the time of thermal contact of the semiconductor wafer with a temperature sensing...
US-7,274,763 Unit for determining the sampling phase
The invention relates to an apparatus and a method for ascertaining and correcting the optimum sampling time for an oversampled input bit stream. This involves...
US-7,274,762 Calculation circuit for calculating a sampling phase error
A calculation circuit for calculating a sampling phase error is provided. According to one aspect, a calculation circuit includes a first delay element chain...
US-7,274,755 Receiver
Receiver for Receiving Data Frames. According to one aspect, a receiver for receiving data frames which contain information data includes a signal input....
US-7,274,597 Method of programming of a non-volatile memory cell comprising steps of applying constant voltage and then...
A method and arrangement are provided for programming an electrically erasable programmable read-only memory cell capable of storing at least one information...
US-7,274,595 Nonvolatile memory device for storing data and method for erasing or programming the same
A method for erasing or programming a nonvolatile memory device comprising a memory cell, a sense amplifier, and a page memory, the method comprising the steps...
US-7,274,312 High rate coding for media noise
An apparatus has a conversion circuit, a precoder circuit, and a selection circuit. The conversion circuit converts user data b.sub.1, b.sub.2, b. . . b.sub.k to...
US-7,274,240 Clock control cell
A clock control cell for production of an output clock signal from an input clock signal has a hold element and an output stage. The hold element is preceded by...
US-7,274,225 Method for driving a semiconductor switching element in a half-bridge and circuit arrangement having a half-bridge
A method and related apparatus drives a first semiconductor switching element, the load path of which is connected in series with a load path of a second...
US-7,274,218 Integrated circuit
An integrated circuit includes a first and a second amplifier circuit (10, 20), which are in each case driven by an input signal (Vin) having a high and a low...
US-7,274,110 Semiconductor component having a CSP housing
The invention relates to a semiconductor component for mounting on a printed circuit board. The semiconductor component includes a housing that at least...
US-7,274,107 Semiconductor device
The present invention relates to semiconductor devices. According to the present invention a semiconductor device is described, comprising: a substrate for...
US-7,274,102 Contacting device, testing method and corresponding production method
A contacting device comprises a carrier device with a first surface, a plurality of first terminal regions on the first surface, at least one elastic elevation...
US-7,274,092 Semiconductor component and method of assembling the same
A semiconductor component includes at least one semiconductor power switch, wherein a gate electrode and at least two source regions are disposed on the upper...
US-7,274,077 Trench transistor
A trench transistor has a cell array, in which at least one cell array trench (2) is provided, and an edge structure framing the cell array. An edge trench (15)...
US-7,274,069 Memory cell
In a memory cell, in a trench, a layer sequence comprising a first oxide layer, a nitride layer provided on the first oxide layer, and a second oxide layer,...
US-7,274,060 Memory cell array and method of forming the same
A memory cell array includes memory cells with storage capacitor and an access transistor. The access transistors are formed in active areas. The memory cell...
US-7,273,821 Method for producing a porous coating
The present invention relates to a process for producing a porous layer adhering to a substrate, which comprises the steps: a. preparation of a composition...
US-7,273,805 Redistribution layer with microstrips
A semiconductor device includes a completed semiconductor chip and a dielectric layer overlying the completed semiconductor chip. A redistribution layer overlies...
US-7,273,790 Method for fabricating trench capacitor with insulation collar electrically connected to substrate through...
Fabricating a trench capacitor with an insulation collar in a substrate, which is electrically connected thereto on one side through a buried contact, in...
US-7,273,786 Method for fabricating a semiconductor memory cell
In order to be able to store information in a non-volatile fashion as compactly and as flexibly as possible in a semiconductor memory cell, the original gate...
US-7,273,638 High density plasma oxidation
A method of oxidizing a substrate having area of about 30,000 mm.sup.2 or more. The surface is preferably comprised of silicon-containing materials, such as...
US-7,273,182 Data storage medium having a test mode
A data storage medium having a memory unit, a control unit, and an interface having contact pads for at least one voltage supply and one data transmission....
US-7,272,757 Method for testing a memory chip and test arrangement
A test arrangement with a test memory chip and a control device is provided. Error correction data are stored in the test memory chip with the aid of the control...
US-7,272,543 Method and computer system for structural analysis and correction of a system of differential equations...
A method for structural analysis and correction of a system of differential equations described by a computer language is disclosed. A description of a physical...
US-7,272,070 Memory access using multiple activated memory cell rows
For one or more disclosed embodiments, a plurality of rows of memory cells in a memory bank are activated, and a column of memory cells in the memory bank is...
US-7,272,063 Memory with a temperature sensor, dynamic memory and memory with a clock unit and method of sensing a...
Methods and apparatus for determining a temperature of a memory device. A memory device includes a memory array, a temperature configured to measure a...
US-7,272,040 Multi-bit virtual-ground NAND memory device
An array of charge-trapping multi-bit memory cells is arranged in a virtual-ground NAND architecture. The memory cells are erased by Fowler-Nordheim tunneling of...
US-7,272,028 MRAM cell with split conductive lines
A magnetoresistive memory cell includes N magnetoresistive elements conductively connected in series (where N is an integer greater than or equal to two). The...
US-7,271,657 Traveling wave amplifier
A traveling wave amplifier comprises a first normally off MOS transistor having a drain, source and gate terminal. The drain terminal is connected to a node of a...
US-7,271,484 Substrate for producing a soldering connection
A solderable device includes a substrate and a soldering pad overlying the substrate. A solder mask overlies the substrate and portions of the soldering pad. The...
US-7,271,472 Circuit board and method for producing a circuit board
A circuit board comprises a dielectric layer, a net of first power supply lines for providing a first reference voltage plane and a net of second power supply...
US-7,271,470 Electronic component having at least two semiconductor power devices
An electronic component includes at least two vertical semiconductor power devices and an electrically conductive contact clip. Each vertical semiconductor...
US-7,271,095 Process for producing metallic interconnects and contact surfaces on electronic components
A process produces metallic interconnects and contact surfaces on electronic components using a copper-nickel-gold layer structure. The copper core of the...
US-7,271,058 Storage capacitor and method of manufacturing a storage capacitor
A storage capacitor suitable for use in a DRAM cell, as well as to a method of manufacturing such a storage capacitor is disclosed. The storage capacitor is...
US-7,271,026 Method for producing chip stacks and chip stacks formed by integrated devices
The method of the present invention relates to a method for producing a chip stack comprising the steps of manufacturing at least a first and a second integrated...
US-7,270,922 Method for determining an edge profile of a volume of a photoresist after a development process
The present invention relates to a method for determining an edge profile of a volume of a photoresist after a development process. At first, the volume of the...
US-7,270,884 Adhesion layer for Pt on SiO.sub.2
Si, Al, Al plus TiN, and IrO2 are used as adhesion layers to prevent peeling of noble metal electrodes, such as Pt, from a silicon dioxide (SiO.sub.2) substrate...
US-7,270,130 Semiconductor device cleaning employing heterogeneous nucleation for controlled cavitation
The present invention provides a method for cleaning semiconductor devices through heterogeneous nucleation of cavitation bubbles. Heterogeneous nucleation is...
US-7,269,777 Decoding apparatus, trellis processor, and method for operating the decoder
A decoding apparatus includes at least one decoder both for a turbo-decoding and for a Viterbi decoding, at least one first data path for the Viterbi decoding of...
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