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Patent # Description
US-7,271,058 Storage capacitor and method of manufacturing a storage capacitor
A storage capacitor suitable for use in a DRAM cell, as well as to a method of manufacturing such a storage capacitor is disclosed. The storage capacitor is...
US-7,271,026 Method for producing chip stacks and chip stacks formed by integrated devices
The method of the present invention relates to a method for producing a chip stack comprising the steps of manufacturing at least a first and a second integrated...
US-7,270,922 Method for determining an edge profile of a volume of a photoresist after a development process
The present invention relates to a method for determining an edge profile of a volume of a photoresist after a development process. At first, the volume of the...
US-7,270,884 Adhesion layer for Pt on SiO.sub.2
Si, Al, Al plus TiN, and IrO2 are used as adhesion layers to prevent peeling of noble metal electrodes, such as Pt, from a silicon dioxide (SiO.sub.2) substrate...
US-7,270,130 Semiconductor device cleaning employing heterogeneous nucleation for controlled cavitation
The present invention provides a method for cleaning semiconductor devices through heterogeneous nucleation of cavitation bubbles. Heterogeneous nucleation is...
US-7,269,777 Decoding apparatus, trellis processor, and method for operating the decoder
A decoding apparatus includes at least one decoder both for a turbo-decoding and for a Viterbi decoding, at least one first data path for the Viterbi decoding of...
US-7,269,742 Microprocessor configuration with encryption
A microcontroller for security applications includes an encryption unit between a bus and a functional unit. The encryption unit includes a gate and a key...
US-7,269,671 Systems, methods and computer program products for leakage-proof program partitioning
Systems, methods and computer program products partition a whole program when it does not fit in a device's memory. Minimal, safe program partitions are...
US-7,269,093 Generating a sampling clock signal in a communication block of a memory device
A method generates a sampling clock signal in a communication block of a memory device having a plurality of communication blocks which are distributed in the...
US-7,269,021 Smart card containing a carrier body for receiving at least one system component having a plurality of...
A smart card contains a carrier body for receiving at least one system component, which has (in each case) a plurality of electrical components, and which unites...
US-7,268,877 Method and apparatus for orienting semiconductor wafers in semiconductor fabrication
Described are systems and methods for orienting a semiconductor wafer during semiconductor fabrication with the aid of an optical alignment system, the...
US-7,268,436 Electronic device with cavity and a method for producing the same
An electronic device can include a top side with circuit structures. The circuit structures form the bottom region of a cavity. Each cavity can be surrounded by...
US-7,268,423 Flexible rewiring plate for semiconductor components, and process for producing it
The present invention describes a rewiring plate for components with connection grids of between approx. 100 nm and 10 .mu.m, which rewiring plate includes a...
US-7,268,383 Capacitor and method of manufacturing a capacitor
Semiconductor devices having capacitors formed of a high-k dielectric and a pair of interconnections on either side of the dielectric are provided along with...
US-7,268,381 Memory cell with trench capacitor and vertical select transistor and an annular contact-making region formed...
The upper capacitor electrode of the trench capacitor is connected to an epitaxially grown source/drain region of the select transistor by a tubular,...
US-7,268,080 Method for printing contacts on a substrate
A method for printing contacts utilizes photolithographic pattern reversal. A negative of the contact is printed on a resist layer. Unexposed portions of the...
US-7,268,079 Method for fabricating a semiconductor having a field zone
A method for fabricating a semiconductor and at least one second semiconductor zone of a semiconductor component having a semiconductor body having a first...
US-7,268,037 Method for fabricating microchips using metal oxide masks
A process for modifying sections of a semiconductor includes covering the sections to remain free of doping with a metal oxide, e.g., aluminum oxide. Then, the...
US-7,266,667 Memory access using multiple sets of address/data lines
Methods and apparatus for accessing multiple memory arrays within a memory device using multiple sets of address/data lines are provided. The memory arrays may...
US-7,266,639 Memory rank decoder for a multi-rank Dual Inline Memory Module (DIMM)
The invention refers to a Memory Rank Decoder for a Multi-Rank Dual Inline Memory Module (DIMM) having a predetermined number of DRAM memory chips mounted on a...
US-7,266,038 Method for activating and deactivating electronic circuit units and circuit arrangement for carrying out the method
The invention provides an electronic circuit arrangement having an electronic circuit module (100) constructed from one or more electronic circuit units...
US-7,266,032 Memory device having low Vpp current consumption
A method of performing a self refresh of memory cells in a memory device. The memory device includes a first group of cell blocks and a second group of cell...
US-7,266,031 Internal voltage generator with temperature control
Methods and apparatus for varying one or more internally generated voltages of a memory device based on the temperature of the memory device are provided. The...
US-7,266,027 Integrated semiconduct memory with test circuit
An integrated semiconductor memory includes word lines connected to a first voltage potential via a respective first controllable switch and a respective third...
US-7,265,585 Method to improve current and slew rate ratio of off-chip drivers
An off-chip driver (OCD) circuit and technique to reduce skew between rising and falling edges of output signals as process conditions vary are provided....
US-7,265,568 Semi-conductor component test process and a system for testing semi-conductor components
A semi-conductor component test process, and a system for testing semi-conductor components, with which several different semi-conductor-component tests can be...
US-7,265,566 Semiconductor component arrangement having a temperature-based defect identification
A semiconductor component arrangement includes a semiconductor body, at least a first power semiconductor switching element, and a defect identification circuit....
US-7,265,564 Method for testing a contact region of a semiconductor module
A method for testing a contact region of a semiconductor module having a circuit arrangement is disclosed. In one embodiment, the semiconductor module is heated...
US-7,265,451 Semiconductor and method for producing a semiconductor
A semiconductor device comprises at least one first semiconductor component being located in a first plane and comprising an active area which has a first...
US-7,265,441 Stackable single package and stacked multi-chip assembly
A stackable packaged chip includes a substrate with a conductive wiring formed therein or thereon. The substrate further includes a plurality of substrate...
US-7,265,424 Fin Field-effect transistor and method for producing a fin field effect-transistor
A fin field effect transistor having a substrate, a fin structure above the substrate, as well as a drain region and a source region outside the fin structure...
US-7,265,413 Semiconductor memory with vertical memory transistors and method for fabricating it
The invention relates to a semiconductor memory having a multiplicity of memory cells and a method for forming the memory cells. The semiconductor memory...
US-7,265,405 Method for fabricating contacts for integrated circuits, and semiconductor component having such contacts
One (or more) contacts are produced on one or more active areas of a semiconductor wafer, it being possible for one or more isolated control lines to be arranged...
US-7,265,381 Opto-electronic memory element on the basis of organic metalloporphyrin molecules
A memory cell for opto-electronic applications includes a substrate, a first electrode and a second electrode, and an active layer arranged between the first and...
US-7,265,376 Non-volatile memory cell, memory cell arrangement and method for production of a non-volatile memory cell
A nonvolatile memory cell, memory cell arrangement, and method for production of a nonvolatile memory cell is disclosed. The nonvolatile memory cell includes a...
US-7,265,025 Method for filling trench and relief geometries in semiconductor structures
A method teaches how to fill trench structures formed in a semiconductor substrate. The trench structures are coated in a first deposition process with a first...
US-7,265,023 Fabrication method for a semiconductor structure
The present invention provides a fabrication method for a semiconductor structure having the steps of providing a semiconductor substrate (1); providing and...
US-7,265,007 Method for fabricating field-effect transistor structures with gate electrodes with a metal layer
Provided is a method for fabricating gate electrode structures each having at least one individual polysilicon layer and a metal layer. A polysilicon layer is...
US-7,263,638 Memory having test circuit
A memory circuit comprises a memory and a first test circuit coupled to the memory. The first test circuit is configured to compare data read from memory cells...
US-7,263,633 Integrated circuit, in particular integrated memory, and methods for operating an integrated circuit
An integrated circuit, in particular, an integrated memory, contains a control circuit for ascertaining an operating state of the circuit. A self-repair circuit,...
US-7,263,604 Heterogeneous parallel multithread processor (HPMT) with local context memory sets for respective processor...
The invention relates to a heterogeneous parallel multithread processor (1) with shared contexts which has a plurality (M) of parallel-connected standard...
US-7,263,599 Thread ID in a multithreaded processor
A multithreaded processor includes a thread ID for each set of fetched bits in an instruction fetch and issue unit. The thread ID attaches to the instructions...
US-7,263,338 Device and method for regulating a transmission moment of a continuous transmission signal
A comparator unit is used to compare an actual transmission time signal with a nominal transmission time signal and to produce a difference signal from the...
US-7,263,121 Method and apparatus for determining a topology of a subscriber line loop
An xDSL modem for data transmission between a central office and a customer device over a subscriber line includes a topology determining unit and a control...
US-7,263,019 Serial presence detect functionality on memory component
Methods and apparatus for accessing serial presence detect data are provided. For some embodiments, serial presence detect logic is incorporated in memory...
US-7,263,011 Memory circuit with flexible bitline-related and/or wordline-related defect memory cell substitution
The inventive memory circuit comprises a main memory block and a substitution memory block for substitution of defect memory cells, with the substitution memory...
US-7,262,850 Method for inspection of periodic grating structures on lithography masks
The invention relates to a method for inspection of periodic structures on lithography masks using a microscope with adjustable illumination and an operating...
US-7,262,837 Noninvasive method for characterizing and identifying embedded micropatterns
The invention relates to a method for noninvasively characterizing embedded micropatterns which are hidden under the surface of a wafer down to 100 .mu.m. The...
US-7,262,723 Compensation circuit for clock jitter compensation
A compensation circuit for a digital/analogue converter, which is clocked by a clock signal comprising a jitter and converts a digital input data signal into an...
US-7,262,456 Bit line structure and production method thereof
The disclosure relates to a bit line structure and an associated production method for the bit line structure. In the bit line structure, at least in a region of...
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