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Patent # Description
US-7,307,868 Integrated circuit including memory cell for storing an information item and method
The invention relates to a memory cell for providing an information item, having a memory element, which has a PMC resistance component with a solid electrolyte...
US-7,307,865 Integrated read-only memory, method for operating said read-only memory and corresponding production method
An integrated read-only memory having select transistors, each of which has a drain connection and an electrode connection for feeding an electrical signal such...
US-7,307,735 Method for determining the depth of a buried structure
The present invention relates to a method for determining the depth of a buried structure in a semiconductor wafer. According to the invention, the layer...
US-7,307,715 Method for the formation of a structure size measured value
The structure size of a structure (100) is measured by forming an auxiliary measured value (Dx', Dy'). A calibration measured value (Px', Py') is determined on...
US-7,307,567 Digital-analog converter and digital-analog conversion method
The present invention provides a digital-analog converter having: a DEM logic device (10) for generating at least two digital output data items (13, 14) from the...
US-7,307,443 Test socket for an integrated circuit
A test socket for an integrated circuit, wherein the test socket has a first plurality of test points for making electrical contact with contacts of a laminate...
US-7,307,346 Final passivation scheme for integrated circuits
A semiconductor device includes a substrate with an active area. A last level interconnect capping layer is disposed over the active area. A buffer layer/crack...
US-7,307,329 Electronic device with guard ring
An electronic device includes a substrate, an insulating layer arranged on the substrate, the insulating layer having an opening in an area of the surface of the...
US-7,307,328 Semiconductor device with temperature sensor
A semiconductor device is disclosed. In one embodiment the semiconductor device includes a semiconductor body of which is integrated a temperature sensor for...
US-7,307,010 Method for processing a thin semiconductor substrate
A method for processing a semiconductor substrate less than 200 .mu.m thick has been provided. The substrate has one or a plurality of semiconductor elements,...
US-7,305,594 Integrated circuit in a maximum input/output configuration
A memory includes input/output paths and electrical leads. Each of the input/output paths are coupled to separate electrical leads. The memory is configured to...
US-7,305,525 Memory system for network broadcasting applications and method for operating the same
A memory system for network broadcasting applications, such as video/audio applications, has at least one memory which is divided into a plurality of addressable...
US-7,305,512 Programme-controlled unit with crossbar employing a diagnostic port
A programme-controlled unit comprises a crossbar with a multiplicity of ports, a multiplicity of devices which are connected to the ports of the crossbar and can...
US-7,305,425 Method and device for digital filtering of interpolated values
In the digital filtering of an input signal (3), which has been produced by interpolation of a pilot signal (2), under certain circumstances numerous values...
US-7,305,216 Transmitting and receiving arrangement with interference signal suppression control
A transmitting and receiving arrangement is disclosed having a transmission path, a reception path, and a control device for suppression of interference signals...
US-7,305,059 Method and device for the clocked output of asynchronously received digital signals
A method and device for the uniform output of asynchronously transmitted digital values is provided, including: receiving the digital values in a receiver from a...
US-7,304,909 Control unit for deactivating and activating the control signals
A control unit is set up to generate and output periodic clock signals, that are in sync with and at the same frequency as a periodic basic clock that is input...
US-7,304,899 Integrated semiconductor memory
An integrated semiconductor memory includes programmable elements, which are arranged in a continuous region on a chip area of the integrated semiconductor...
US-7,304,879 Non-volatile memory element capable of storing irreversible complementary data
A non-volatile memory element for storing at least one data item, having a readable memory cell which can be written on with a first part of a data item, the...
US-7,304,721 Method for dynamically monitoring a reticle
The method of dynamically monitoring a reticle includes preventively macro monitoring and defect inspecting with regard to mechanical loading, including particle...
US-7,304,716 Method for purging an optical lens
By a unit for determining fractions of a substance in a gas or gas mixture, measurements are carried out on the gas or gas mixture for purging a lens in a...
US-7,304,598 Shared amplifier circuit
A circuit has a first amplifier having first positive and negative inputs and a second amplifier having second positive and negative inputs. A first unit is...
US-7,304,546 Control loop filter
A feedback control loop having a filter response and a cut-off frequency comprises a system under control for generating an output signal being an output signal...
US-7,304,534 Amplifier arrangement, and method for compensating for an offset
An amplifier arrangement and a method for compensating for an offset in an amplifier is provided. A respective switch for connecting together the inputs in a...
US-7,304,525 Level converter
A level converter is disclosed. In one embodiment, the level converter includes a first and second input for applying a first voltage and first and second output...
US-7,304,519 Data latch, master/slave flipflop and frequency divider circuit
A data latch contains a supply connection, a reference ground potential connection and a data input. The input side of an inverter is connected to the data...
US-7,304,517 Duty cycle corrector
A duty cycle corrector, including a first, second circuit and a third circuit is disclosed. The third circuit is configured to obtain a threshold value in...
US-7,304,515 Device to be used in the synchronization of clock pulses, as well as a clock pulse synchronization process
The invention involves a clock pulse synchronization process as well as a device to be used in the synchronization of clock pulses, including a first delay...
US-7,304,495 Pseudodynamic off-chip driver calibration
A driver system, a driver calibration circuit arrangement for calibration of an impedance of a driver circuit arrangement, and a method for calibration of an...
US-7,304,349 Power semiconductor component with increased robustness
The invention relates to a power semiconductor component with increased robustness, in which a contact layer (13, 14) applied directly to a main surface (7, 11)...
US-7,304,342 Semiconductor memory cell and associated fabrication method
A semiconductor memory cell and an associated fabrication method are provided in which a storage capacitor is connected to a selection transistor. The storage...
US-7,303,970 Method of fabricating dielectric mixed layers and capacitive element and use thereof
The present invention provides a method for fabricating a capacitive element (100), a substrate (101) being provided as a first electrode layer of the capacitive...
US-7,303,961 Method for producing a junction region between a trench and a semiconductor zone surrounding the trench
A method for producing a junction region (2, 5, 6, 7) between a trench (3) and a semiconductor zone (2) surrounding the trench (3) in a trench semiconductor...
US-7,303,940 Semiconductor component having at least one organic semiconductor layer and method for fabricating the same
A semiconductor component has at least one organic semiconductor layer. The component also includes at least one protective layer for at least partially covering...
US-7,302,622 Integrated memory having a test circuit for functional testing of the memory
An integrated memory having a plurality of memory banks includes a test circuit for functional testing of the memory. A plurality of secondary sense amplifiers...
US-7,302,357 Concept for compensating piezo-influences on an integrated semiconductor circuit
A compensation signal, which derives the mechanical stress, which acts on an integrated semiconductor circuit, from two partial compensation signals, which are...
US-7,302,046 Method for the detection of impedances and for the qualification of the telephone lines
The invention relates to a method for detection of impedances, in particular along inductances, in telephone lines of the type with two metal wires as signal...
US-7,301,799 Memory cell array
A memory cell array is formed by providing a plurality of memory cells along a substrate, where each of the memory cells includes a storage element and an access...
US-7,301,779 Electronic chip and electronic chip assembly
A multiplicity of nanotubes are applied to at least one external chip metal contact of an electronic chip in order to make contact between the electronic chip...
US-7,301,411 Voltage-controlled oscillator circuit with analogue and digital actuation
A VCO circuit (20) has a coil (21) and, in parallel therewith, a constant capacitance (24) and adjustable capacitance elements (22, 23). A first capacitance...
US-7,301,376 Control circuit and method for driving a half-bridge circuit
A method is disclosed for controlling a first transistor in a half-bridge circuit which also includes a second transistor. The transistors can be controlled by...
US-7,301,353 Sensor element for providing a sensor signal, and method for operating a sensor element
A method for operating a sensor element having two contact terminal pairs, comprises steps of providing a first measurement value by applying a first controlled...
US-7,301,318 Circuit arrangement for voltage adjustment
A circuit arrangement for voltage regulation having a series regulator with a regulating amplifier and a charge pump that is connected downstream of the...
US-7,301,204 SOI component with increased dielectric strength and improved heat dissipation
A semiconductor component arrangement comprises a semiconductor substrate of a first conduction type, an insulation layer arranged on the substrate, and a...
US-7,301,192 Dram cell pair and dram memory cell array
Stack and trench memory cells are provided in a DRAM memory cell array. The stack and trench memory cells are arranged so as to form identical cell pairs each...
US-7,300,875 Post metal chemical mechanical polishing dry cleaning
Metal residue on a semiconductor surface resulting from metal chemical mechanical polishing ("CMP") process are eradicated using a dry clean process. The dry...
US-7,300,855 Reversible oxidation protection of microcomponents
In a method for the reversible oxidation protection of microcomponents, a substrate is provided, a silicon nitride layer is provided on the substrate in order to...
US-7,300,823 Apparatus for housing a micromechanical structure and method for producing the same
Apparatus for housing a micromechanical structure, and a method for producing the housing. The apparatus has a substrate having a main side on which the...
US-7,299,447 Method of testing a mapping of an electrical circuit
An electrical circuit can be described with a reference model that has a plurality of states and a plurality of state transitions. Acceptable and/or unacceptable...
US-7,299,388 Method and apparatus for selectively accessing and configuring individual chips of a semi-conductor wafer
A method and apparatus according to the present invention enable wafer chips to be configured with a single power on and off sequence and further enable a chip...
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