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Patent # Description
US-7,265,585 Method to improve current and slew rate ratio of off-chip drivers
An off-chip driver (OCD) circuit and technique to reduce skew between rising and falling edges of output signals as process conditions vary are provided....
US-7,265,568 Semi-conductor component test process and a system for testing semi-conductor components
A semi-conductor component test process, and a system for testing semi-conductor components, with which several different semi-conductor-component tests can be...
US-7,265,566 Semiconductor component arrangement having a temperature-based defect identification
A semiconductor component arrangement includes a semiconductor body, at least a first power semiconductor switching element, and a defect identification circuit....
US-7,265,564 Method for testing a contact region of a semiconductor module
A method for testing a contact region of a semiconductor module having a circuit arrangement is disclosed. In one embodiment, the semiconductor module is heated...
US-7,265,451 Semiconductor and method for producing a semiconductor
A semiconductor device comprises at least one first semiconductor component being located in a first plane and comprising an active area which has a first...
US-7,265,441 Stackable single package and stacked multi-chip assembly
A stackable packaged chip includes a substrate with a conductive wiring formed therein or thereon. The substrate further includes a plurality of substrate...
US-7,265,424 Fin Field-effect transistor and method for producing a fin field effect-transistor
A fin field effect transistor having a substrate, a fin structure above the substrate, as well as a drain region and a source region outside the fin structure...
US-7,265,413 Semiconductor memory with vertical memory transistors and method for fabricating it
The invention relates to a semiconductor memory having a multiplicity of memory cells and a method for forming the memory cells. The semiconductor memory...
US-7,265,405 Method for fabricating contacts for integrated circuits, and semiconductor component having such contacts
One (or more) contacts are produced on one or more active areas of a semiconductor wafer, it being possible for one or more isolated control lines to be arranged...
US-7,265,381 Opto-electronic memory element on the basis of organic metalloporphyrin molecules
A memory cell for opto-electronic applications includes a substrate, a first electrode and a second electrode, and an active layer arranged between the first and...
US-7,265,376 Non-volatile memory cell, memory cell arrangement and method for production of a non-volatile memory cell
A nonvolatile memory cell, memory cell arrangement, and method for production of a nonvolatile memory cell is disclosed. The nonvolatile memory cell includes a...
US-7,265,025 Method for filling trench and relief geometries in semiconductor structures
A method teaches how to fill trench structures formed in a semiconductor substrate. The trench structures are coated in a first deposition process with a first...
US-7,265,023 Fabrication method for a semiconductor structure
The present invention provides a fabrication method for a semiconductor structure having the steps of providing a semiconductor substrate (1); providing and...
US-7,265,007 Method for fabricating field-effect transistor structures with gate electrodes with a metal layer
Provided is a method for fabricating gate electrode structures each having at least one individual polysilicon layer and a metal layer. A polysilicon layer is...
US-7,263,638 Memory having test circuit
A memory circuit comprises a memory and a first test circuit coupled to the memory. The first test circuit is configured to compare data read from memory cells...
US-7,263,633 Integrated circuit, in particular integrated memory, and methods for operating an integrated circuit
An integrated circuit, in particular, an integrated memory, contains a control circuit for ascertaining an operating state of the circuit. A self-repair circuit,...
US-7,263,604 Heterogeneous parallel multithread processor (HPMT) with local context memory sets for respective processor...
The invention relates to a heterogeneous parallel multithread processor (1) with shared contexts which has a plurality (M) of parallel-connected standard...
US-7,263,599 Thread ID in a multithreaded processor
A multithreaded processor includes a thread ID for each set of fetched bits in an instruction fetch and issue unit. The thread ID attaches to the instructions...
US-7,263,338 Device and method for regulating a transmission moment of a continuous transmission signal
A comparator unit is used to compare an actual transmission time signal with a nominal transmission time signal and to produce a difference signal from the...
US-7,263,121 Method and apparatus for determining a topology of a subscriber line loop
An xDSL modem for data transmission between a central office and a customer device over a subscriber line includes a topology determining unit and a control...
US-7,263,019 Serial presence detect functionality on memory component
Methods and apparatus for accessing serial presence detect data are provided. For some embodiments, serial presence detect logic is incorporated in memory...
US-7,263,011 Memory circuit with flexible bitline-related and/or wordline-related defect memory cell substitution
The inventive memory circuit comprises a main memory block and a substitution memory block for substitution of defect memory cells, with the substitution memory...
US-7,262,850 Method for inspection of periodic grating structures on lithography masks
The invention relates to a method for inspection of periodic structures on lithography masks using a microscope with adjustable illumination and an operating...
US-7,262,837 Noninvasive method for characterizing and identifying embedded micropatterns
The invention relates to a method for noninvasively characterizing embedded micropatterns which are hidden under the surface of a wafer down to 100 .mu.m. The...
US-7,262,723 Compensation circuit for clock jitter compensation
A compensation circuit for a digital/analogue converter, which is clocked by a clock signal comprising a jitter and converts a digital input data signal into an...
US-7,262,456 Bit line structure and production method thereof
The disclosure relates to a bit line structure and an associated production method for the bit line structure. In the bit line structure, at least in a region of...
US-7,262,118 Method for generating a structure on a substrate
The invention relates to a method for generating very short gate structures. In a method for generating a structure on a substrate in accordance with one...
US-7,261,829 Method for masking a recess in a structure having a high aspect ratio
A method for selective masking is described. In this case, a filling material is applied to a structure which, as a function of the aspect ratio of the...
US-RE39,799 Memory cell array and method for manufacturing it
In a storage cell array, a first and a second line are provided which have a crossing point, at which a storage element with magnetoresistive effect is disposed....
US-7,260,734 Method and circuit for transmitting data between systems having different clock speeds
In order to carry out an equidistant data transfer between clock domains having different clock rates, a combination of a counter (1) and a finite state machine...
US-7,260,707 Variable length instruction pipeline
A variable length instruction pipeline includes optional expansion stages that can be included in the variable length instruction pipeline to avoid pipeline...
US-7,260,690 Microprocessor circuit for data carriers and method for organizing access to data stored in a memory
A microprocessor circuit for organizing access to data or programs stored in a memory has a microprocessor, a memory for storing an operating system, and a...
US-7,260,671 Information containing means for memory modules and memory chips
A memory module includes at least one memory chip arranged on the memory module. Information about the memory module and/or the at least one memory chip arranged...
US-7,260,490 Method for measuring a delay time of a digital circuit and corresponding device and digital circuit
In a method and device measuring a delay time of a section of a digital circuit, an output signal of the section is saved in different memory locations with a...
US-7,260,413 Data transmission system having a high data transmission rate and method of transmitting the data
A data transmission system has a base station and at least one mobile station. Data packets are interchanged between the base station and the mobile station...
US-7,260,359 Method for transmission of data between a master station and a slave station, and a data transmission system
Method for transmission of data between a master station and a slave station, and a data transmission systemData slots are interchanged in accordance with a time...
US-7,259,993 Reference scheme for a non-volatile semiconductor memory device
A non-volatile semiconductor memory device is provided comprising a memory area and a circuitry area. The memory area includes a plurality of memory cells and a...
US-7,259,607 Integrated semiconductor memory with clock generation
An integrated semiconductor memory includes a clock generator circuit driven by an external clock signal and a control circuit driven by the external clock...
US-7,259,579 Method and apparatus for semiconductor testing utilizing dies with integrated circuit
A method and apparatus for testing semiconductor wafers in which certain contact areas of dies not used in the testing and required to be at a predetermined...
US-7,259,441 Hollow structure in an integrated circuit and method for producing such a hollow structure in an integrated circuit
A pattern of voids in an integrated circuit having a first layer, a first layer surface and adjacent lands on the first layer surface, the adjacent lands...
US-7,259,107 Method of forming isolated features of semiconductor devices
A method of forming isolated features of semiconductor devices is disclosed. A first hard mask is deposited over a material layer to be patterned, and a second...
US-7,259,088 Apparatus for singulating and bonding semiconductor chips, and method for the same
An apparatus for singulating and bonding semiconductor chips includes a singulating station and a mounting station. In the singulating station, a semiconductor...
US-7,259,061 Method for forming a capacitor for an integrated circuit and integrated circuit
Integrated circuits can include an integrated capacitor with a metal alloy layer. Methods for forming such integrated circuits can include providing a substrate,...
US-7,259,060 Method for fabricating a semiconductor structure
A method fabricates a semiconductor structure having a plurality of memory cells that are provided in a semiconductor substrate of a first conductivity type and...
US-7,259,025 Ferromagnetic liner for conductive lines of magnetic memory cells
A method of forming a ferromagnetic liner on conductive lines of magnetic memory devices and a structure thereof. The ferromagnetic liner increases the flux...
US-7,259,024 Method of treating a substrate in manufacturing a magnetoresistive memory cell
A method of treating a substrate in manufacturing a magnetoresistive memory cell includes performing a cleaning operation on the substrate using a mask layer as...
US-7,257,222 Ring voltage generation circuit and method for generating a ring voltage
The present invention relates to a ring voltage generation circuit for generating a ring voltage (VTR) between a TIP lead (9) and a RING lead (10) with minimized...
US-7,257,038 Test mode for IPP current measurement for wordline defect detection
A semiconductor integrated circuit memory device, and test method for a memory device are provided in which an external wordline voltage is applied to a wordline...
US-7,257,031 Circuit arrangement and method for switching high-voltage signals by means of low-voltage signals
The invention relates to a circuit arrangement for switching high-voltage signals with low-voltage signals, particularly for driving a semiconductor memory...
US-7,257,014 PMC memory circuit and method for storing a datum in a PMC memory circuit
The invention relates to a PMC memory circuit comprising a PMC memory cell having a PMC component, the PMC component having a solid electrolyte with permanently...
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