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Patent # Description
US-7,274,225 Method for driving a semiconductor switching element in a half-bridge and circuit arrangement having a half-bridge
A method and related apparatus drives a first semiconductor switching element, the load path of which is connected in series with a load path of a second...
US-7,274,218 Integrated circuit
An integrated circuit includes a first and a second amplifier circuit (10, 20), which are in each case driven by an input signal (Vin) having a high and a low...
US-7,274,110 Semiconductor component having a CSP housing
The invention relates to a semiconductor component for mounting on a printed circuit board. The semiconductor component includes a housing that at least...
US-7,274,107 Semiconductor device
The present invention relates to semiconductor devices. According to the present invention a semiconductor device is described, comprising: a substrate for...
US-7,274,102 Contacting device, testing method and corresponding production method
A contacting device comprises a carrier device with a first surface, a plurality of first terminal regions on the first surface, at least one elastic elevation...
US-7,274,092 Semiconductor component and method of assembling the same
A semiconductor component includes at least one semiconductor power switch, wherein a gate electrode and at least two source regions are disposed on the upper...
US-7,274,077 Trench transistor
A trench transistor has a cell array, in which at least one cell array trench (2) is provided, and an edge structure framing the cell array. An edge trench (15)...
US-7,274,069 Memory cell
In a memory cell, in a trench, a layer sequence comprising a first oxide layer, a nitride layer provided on the first oxide layer, and a second oxide layer,...
US-7,274,060 Memory cell array and method of forming the same
A memory cell array includes memory cells with storage capacitor and an access transistor. The access transistors are formed in active areas. The memory cell...
US-7,273,821 Method for producing a porous coating
The present invention relates to a process for producing a porous layer adhering to a substrate, which comprises the steps: a. preparation of a composition...
US-7,273,805 Redistribution layer with microstrips
A semiconductor device includes a completed semiconductor chip and a dielectric layer overlying the completed semiconductor chip. A redistribution layer overlies...
US-7,273,790 Method for fabricating trench capacitor with insulation collar electrically connected to substrate through...
Fabricating a trench capacitor with an insulation collar in a substrate, which is electrically connected thereto on one side through a buried contact, in...
US-7,273,786 Method for fabricating a semiconductor memory cell
In order to be able to store information in a non-volatile fashion as compactly and as flexibly as possible in a semiconductor memory cell, the original gate...
US-7,273,638 High density plasma oxidation
A method of oxidizing a substrate having area of about 30,000 mm.sup.2 or more. The surface is preferably comprised of silicon-containing materials, such as...
US-7,273,182 Data storage medium having a test mode
A data storage medium having a memory unit, a control unit, and an interface having contact pads for at least one voltage supply and one data transmission....
US-7,272,757 Method for testing a memory chip and test arrangement
A test arrangement with a test memory chip and a control device is provided. Error correction data are stored in the test memory chip with the aid of the control...
US-7,272,543 Method and computer system for structural analysis and correction of a system of differential equations...
A method for structural analysis and correction of a system of differential equations described by a computer language is disclosed. A description of a physical...
US-7,272,070 Memory access using multiple activated memory cell rows
For one or more disclosed embodiments, a plurality of rows of memory cells in a memory bank are activated, and a column of memory cells in the memory bank is...
US-7,272,063 Memory with a temperature sensor, dynamic memory and memory with a clock unit and method of sensing a...
Methods and apparatus for determining a temperature of a memory device. A memory device includes a memory array, a temperature configured to measure a...
US-7,272,040 Multi-bit virtual-ground NAND memory device
An array of charge-trapping multi-bit memory cells is arranged in a virtual-ground NAND architecture. The memory cells are erased by Fowler-Nordheim tunneling of...
US-7,272,028 MRAM cell with split conductive lines
A magnetoresistive memory cell includes N magnetoresistive elements conductively connected in series (where N is an integer greater than or equal to two). The...
US-7,271,657 Traveling wave amplifier
A traveling wave amplifier comprises a first normally off MOS transistor having a drain, source and gate terminal. The drain terminal is connected to a node of a...
US-7,271,484 Substrate for producing a soldering connection
A solderable device includes a substrate and a soldering pad overlying the substrate. A solder mask overlies the substrate and portions of the soldering pad. The...
US-7,271,472 Circuit board and method for producing a circuit board
A circuit board comprises a dielectric layer, a net of first power supply lines for providing a first reference voltage plane and a net of second power supply...
US-7,271,470 Electronic component having at least two semiconductor power devices
An electronic component includes at least two vertical semiconductor power devices and an electrically conductive contact clip. Each vertical semiconductor...
US-7,271,095 Process for producing metallic interconnects and contact surfaces on electronic components
A process produces metallic interconnects and contact surfaces on electronic components using a copper-nickel-gold layer structure. The copper core of the...
US-7,271,058 Storage capacitor and method of manufacturing a storage capacitor
A storage capacitor suitable for use in a DRAM cell, as well as to a method of manufacturing such a storage capacitor is disclosed. The storage capacitor is...
US-7,271,026 Method for producing chip stacks and chip stacks formed by integrated devices
The method of the present invention relates to a method for producing a chip stack comprising the steps of manufacturing at least a first and a second integrated...
US-7,270,922 Method for determining an edge profile of a volume of a photoresist after a development process
The present invention relates to a method for determining an edge profile of a volume of a photoresist after a development process. At first, the volume of the...
US-7,270,884 Adhesion layer for Pt on SiO.sub.2
Si, Al, Al plus TiN, and IrO2 are used as adhesion layers to prevent peeling of noble metal electrodes, such as Pt, from a silicon dioxide (SiO.sub.2) substrate...
US-7,270,130 Semiconductor device cleaning employing heterogeneous nucleation for controlled cavitation
The present invention provides a method for cleaning semiconductor devices through heterogeneous nucleation of cavitation bubbles. Heterogeneous nucleation is...
US-7,269,777 Decoding apparatus, trellis processor, and method for operating the decoder
A decoding apparatus includes at least one decoder both for a turbo-decoding and for a Viterbi decoding, at least one first data path for the Viterbi decoding of...
US-7,269,742 Microprocessor configuration with encryption
A microcontroller for security applications includes an encryption unit between a bus and a functional unit. The encryption unit includes a gate and a key...
US-7,269,671 Systems, methods and computer program products for leakage-proof program partitioning
Systems, methods and computer program products partition a whole program when it does not fit in a device's memory. Minimal, safe program partitions are...
US-7,269,093 Generating a sampling clock signal in a communication block of a memory device
A method generates a sampling clock signal in a communication block of a memory device having a plurality of communication blocks which are distributed in the...
US-7,269,021 Smart card containing a carrier body for receiving at least one system component having a plurality of...
A smart card contains a carrier body for receiving at least one system component, which has (in each case) a plurality of electrical components, and which unites...
US-7,268,877 Method and apparatus for orienting semiconductor wafers in semiconductor fabrication
Described are systems and methods for orienting a semiconductor wafer during semiconductor fabrication with the aid of an optical alignment system, the...
US-7,268,436 Electronic device with cavity and a method for producing the same
An electronic device can include a top side with circuit structures. The circuit structures form the bottom region of a cavity. Each cavity can be surrounded by...
US-7,268,423 Flexible rewiring plate for semiconductor components, and process for producing it
The present invention describes a rewiring plate for components with connection grids of between approx. 100 nm and 10 .mu.m, which rewiring plate includes a...
US-7,268,383 Capacitor and method of manufacturing a capacitor
Semiconductor devices having capacitors formed of a high-k dielectric and a pair of interconnections on either side of the dielectric are provided along with...
US-7,268,381 Memory cell with trench capacitor and vertical select transistor and an annular contact-making region formed...
The upper capacitor electrode of the trench capacitor is connected to an epitaxially grown source/drain region of the select transistor by a tubular,...
US-7,268,080 Method for printing contacts on a substrate
A method for printing contacts utilizes photolithographic pattern reversal. A negative of the contact is printed on a resist layer. Unexposed portions of the...
US-7,268,079 Method for fabricating a semiconductor having a field zone
A method for fabricating a semiconductor and at least one second semiconductor zone of a semiconductor component having a semiconductor body having a first...
US-7,268,037 Method for fabricating microchips using metal oxide masks
A process for modifying sections of a semiconductor includes covering the sections to remain free of doping with a metal oxide, e.g., aluminum oxide. Then, the...
US-7,266,667 Memory access using multiple sets of address/data lines
Methods and apparatus for accessing multiple memory arrays within a memory device using multiple sets of address/data lines are provided. The memory arrays may...
US-7,266,639 Memory rank decoder for a multi-rank Dual Inline Memory Module (DIMM)
The invention refers to a Memory Rank Decoder for a Multi-Rank Dual Inline Memory Module (DIMM) having a predetermined number of DRAM memory chips mounted on a...
US-7,266,038 Method for activating and deactivating electronic circuit units and circuit arrangement for carrying out the method
The invention provides an electronic circuit arrangement having an electronic circuit module (100) constructed from one or more electronic circuit units...
US-7,266,032 Memory device having low Vpp current consumption
A method of performing a self refresh of memory cells in a memory device. The memory device includes a first group of cell blocks and a second group of cell...
US-7,266,031 Internal voltage generator with temperature control
Methods and apparatus for varying one or more internally generated voltages of a memory device based on the temperature of the memory device are provided. The...
US-7,266,027 Integrated semiconduct memory with test circuit
An integrated semiconductor memory includes word lines connected to a first voltage potential via a respective first controllable switch and a respective third...
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