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Data storage medium having a test mode
A data storage medium having a memory unit, a control unit, and an interface having contact pads for at least one voltage supply and one data transmission....
Method for testing a memory chip and test arrangement
A test arrangement with a test memory chip and a control device is provided. Error correction data are stored in the test memory chip with the aid of the control...
Method and computer system for structural analysis and correction of a
system of differential equations...
A method for structural analysis and correction of a system of differential equations described by a computer language is disclosed. A description of a physical...
Memory access using multiple activated memory cell rows
For one or more disclosed embodiments, a plurality of rows of memory cells in a memory bank are activated, and a column of memory cells in the memory bank is...
Memory with a temperature sensor, dynamic memory and memory with a clock
unit and method of sensing a...
Methods and apparatus for determining a temperature of a memory device. A memory device includes a memory array, a temperature configured to measure a...
Multi-bit virtual-ground NAND memory device
An array of charge-trapping multi-bit memory cells is arranged in a virtual-ground NAND architecture. The memory cells are erased by Fowler-Nordheim tunneling of...
MRAM cell with split conductive lines
A magnetoresistive memory cell includes N magnetoresistive elements conductively connected in series (where N is an integer greater than or equal to two). The...
Traveling wave amplifier
A traveling wave amplifier comprises a first normally off MOS transistor having a drain, source and gate terminal. The drain terminal is connected to a node of a...
Substrate for producing a soldering connection
A solderable device includes a substrate and a soldering pad overlying the substrate. A solder mask overlies the substrate and portions of the soldering pad. The...
Circuit board and method for producing a circuit board
A circuit board comprises a dielectric layer, a net of first power supply lines for providing a first reference voltage plane and a net of second power supply...
Electronic component having at least two semiconductor power devices
An electronic component includes at least two vertical semiconductor power devices and an electrically conductive contact clip. Each vertical semiconductor...
Process for producing metallic interconnects and contact surfaces on
A process produces metallic interconnects and contact surfaces on electronic components using a copper-nickel-gold layer structure. The copper core of the...
Storage capacitor and method of manufacturing a storage capacitor
A storage capacitor suitable for use in a DRAM cell, as well as to a method of manufacturing such a storage capacitor is disclosed. The storage capacitor is...
Method for producing chip stacks and chip stacks formed by integrated
The method of the present invention relates to a method for producing a chip stack comprising the steps of manufacturing at least a first and a second integrated...
Method for determining an edge profile of a volume of a photoresist after
a development process
The present invention relates to a method for determining an edge profile of a volume of a photoresist after a development process. At first, the volume of the...
Adhesion layer for Pt on SiO.sub.2
Si, Al, Al plus TiN, and IrO2 are used as adhesion layers to prevent peeling of noble metal electrodes, such as Pt, from a silicon dioxide (SiO.sub.2) substrate...
Semiconductor device cleaning employing heterogeneous nucleation for
The present invention provides a method for cleaning semiconductor devices through heterogeneous nucleation of cavitation bubbles. Heterogeneous nucleation is...
Decoding apparatus, trellis processor, and method for operating the
A decoding apparatus includes at least one decoder both for a turbo-decoding and for a Viterbi decoding, at least one first data path for the Viterbi decoding of...
Microprocessor configuration with encryption
A microcontroller for security applications includes an encryption unit between a bus and a functional unit. The encryption unit includes a gate and a key...
Systems, methods and computer program products for leakage-proof program
Systems, methods and computer program products partition a whole program when it does not fit in a device's memory. Minimal, safe program partitions are...
Generating a sampling clock signal in a communication block of a memory
A method generates a sampling clock signal in a communication block of a memory device having a plurality of communication blocks which are distributed in the...
Smart card containing a carrier body for receiving at least one system
component having a plurality of...
A smart card contains a carrier body for receiving at least one system component, which has (in each case) a plurality of electrical components, and which unites...
Method and apparatus for orienting semiconductor wafers in semiconductor
Described are systems and methods for orienting a semiconductor wafer during semiconductor fabrication with the aid of an optical alignment system, the...
Electronic device with cavity and a method for producing the same
An electronic device can include a top side with circuit structures. The circuit structures form the bottom region of a cavity. Each cavity can be surrounded by...
Flexible rewiring plate for semiconductor components, and process for
The present invention describes a rewiring plate for components with connection grids of between approx. 100 nm and 10 .mu.m, which rewiring plate includes a...
Capacitor and method of manufacturing a capacitor
Semiconductor devices having capacitors formed of a high-k dielectric and a pair of interconnections on either side of the dielectric are provided along with...
Memory cell with trench capacitor and vertical select transistor and an
annular contact-making region formed...
The upper capacitor electrode of the trench capacitor is connected to an epitaxially grown source/drain region of the select transistor by a tubular,...
Method for printing contacts on a substrate
A method for printing contacts utilizes photolithographic pattern reversal. A negative of the contact is printed on a resist layer. Unexposed portions of the...
Method for fabricating a semiconductor having a field zone
A method for fabricating a semiconductor and at least one second semiconductor zone of a semiconductor component having a semiconductor body having a first...
Method for fabricating microchips using metal oxide masks
A process for modifying sections of a semiconductor includes covering the sections to remain free of doping with a metal oxide, e.g., aluminum oxide. Then, the...
Memory access using multiple sets of address/data lines
Methods and apparatus for accessing multiple memory arrays within a memory device using multiple sets of address/data lines are provided. The memory arrays may...
Memory rank decoder for a multi-rank Dual Inline Memory Module (DIMM)
The invention refers to a Memory Rank Decoder for a Multi-Rank Dual Inline Memory Module (DIMM) having a predetermined number of DRAM memory chips mounted on a...
Method for activating and deactivating electronic circuit units and
circuit arrangement for carrying out the method
The invention provides an electronic circuit arrangement having an electronic circuit module (100) constructed from one or more electronic circuit units...
Memory device having low Vpp current consumption
A method of performing a self refresh of memory cells in a memory device. The memory device includes a first group of cell blocks and a second group of cell...
Internal voltage generator with temperature control
Methods and apparatus for varying one or more internally generated voltages of a memory device based on the temperature of the memory device are provided. The...
Integrated semiconduct memory with test circuit
An integrated semiconductor memory includes word lines connected to a first voltage potential via a respective first controllable switch and a respective third...
Method to improve current and slew rate ratio of off-chip drivers
An off-chip driver (OCD) circuit and technique to reduce skew between rising and falling edges of output signals as process conditions vary are provided....
Semi-conductor component test process and a system for testing
A semi-conductor component test process, and a system for testing semi-conductor components, with which several different semi-conductor-component tests can be...
Semiconductor component arrangement having a temperature-based defect
A semiconductor component arrangement includes a semiconductor body, at least a first power semiconductor switching element, and a defect identification circuit....
Method for testing a contact region of a semiconductor module
A method for testing a contact region of a semiconductor module having a circuit arrangement is disclosed. In one embodiment, the semiconductor module is heated...
Semiconductor and method for producing a semiconductor
A semiconductor device comprises at least one first semiconductor component being located in a first plane and comprising an active area which has a first...
Stackable single package and stacked multi-chip assembly
A stackable packaged chip includes a substrate with a conductive wiring formed therein or thereon. The substrate further includes a plurality of substrate...
Fin Field-effect transistor and method for producing a fin field
A fin field effect transistor having a substrate, a fin structure above the substrate, as well as a drain region and a source region outside the fin structure...
Semiconductor memory with vertical memory transistors and method for
The invention relates to a semiconductor memory having a multiplicity of memory cells and a method for forming the memory cells. The semiconductor memory...
Method for fabricating contacts for integrated circuits, and semiconductor
component having such contacts
One (or more) contacts are produced on one or more active areas of a semiconductor wafer, it being possible for one or more isolated control lines to be arranged...
Opto-electronic memory element on the basis of organic metalloporphyrin
A memory cell for opto-electronic applications includes a substrate, a first electrode and a second electrode, and an active layer arranged between the first and...
Non-volatile memory cell, memory cell arrangement and method for
production of a non-volatile memory cell
A nonvolatile memory cell, memory cell arrangement, and method for production of a nonvolatile memory cell is disclosed. The nonvolatile memory cell includes a...
Method for filling trench and relief geometries in semiconductor
A method teaches how to fill trench structures formed in a semiconductor substrate. The trench structures are coated in a first deposition process with a first...
Fabrication method for a semiconductor structure
The present invention provides a fabrication method for a semiconductor structure having the steps of providing a semiconductor substrate (1); providing and...
Method for fabricating field-effect transistor structures with gate
electrodes with a metal layer
Provided is a method for fabricating gate electrode structures each having at least one individual polysilicon layer and a metal layer. A polysilicon layer is...