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Patent # Description
US-7,340,539 Device connected to a bus for storing information utilized to allocate priority to data stored in storage...
A device that is connected to a bus can transmit data to one or more other devices and/or can receive data from other devices, through the bus, includes storage...
US-7,340,313 Monitoring device for monitoring internal signals during initialization of an electronic circuit
The invention provides a device for monitoring electronic circuit units during an initialization phase. The device has at least one internal data line (103) for...
US-7,340,257 Maximum likelihood estimation of the channel coefficients and of the DC offset in a digital baseband signal of...
The proposed iterative method concurrently calculates maximum likelihood estimated values for the channel coefficients (h.sub.0, . . . , h.sub.L; .theta..sub.h)...
US-7,340,224 Devices for reducing the dynamic range of signals in transmitters of communication systems
A device reduces the dynamic range of a signal at a first point along a signal processing direction in a transmitter of a communication system. The device...
US-7,339,987 Device for correcting a receiving signal
The invention relates to a device for correcting a receiver signal which is associated with an emission signal transmitted in a distorted transmission system....
US-7,339,841 Test mode method and apparatus for internal memory timing signals
A method of testing internal signals of a memory for timing marginalities which may result in unstable operation includes: delaying internal address signals of...
US-7,339,840 Memory system and method of accessing memory chips of a memory system
A memory system and method is discussed. The memory system includes a memory controller and at least one memory module on which a certain number of semiconductor...
US-7,339,837 Configurable embedded processor
A configurable processor architecture uses a common simulation database for multiple processor configurations to reduce the cost of producing customized...
US-7,339,814 Phase change memory array having equalized resistance
A memory includes memory cells, a first line coupled to the memory cells, and a second line coupled to the memory cells. A series resistance due of the first...
US-7,339,773 Method for driving a semiconductor switch and circuit configuration with a semiconductor switch
A method for driving a semiconductor switch with load current limiting and thermal protection whose maximum load current is limited and which switches off when a...
US-7,339,652 Apparatus for projecting a pattern into an image plane
An improvement of the imaging quality with simultaneous transfer of line-space gratings and peripheral structures including a MUX space is achieved using a...
US-7,339,445 BAW duplexer without phase shifter
A duplexer for connection with an antenna comprises an antenna port, a transmitting filter comprising bulk acoustic wave (BAW) resonators having a first antenna...
US-7,339,419 Filter circuit array
A filter circuit array is disclosed. In one embodiment, the filter circuit array includes a higher-order filter circuit array, wherein one energy storage per...
US-7,339,415 SC circuit arrangement
The invention relates to a linear SC circuit arrangement using integrated deep submicron technology, having at least one switched capacitor circuit which is...
US-7,339,407 DLL circuit for providing an adjustable phase relationship with respect to a periodic input signal
The invention relates to a DLL circuit for providing an adjustable time delay of a periodic input signal, said circuit having controllable delay elements which...
US-7,339,393 Gate drive circuit for an insulated gate power transistor
The invention relates to a gate drive circuit for, and in combination with, an insulated gate power transistor. The drive circuit is connected to the gate...
US-7,339,358 Switching converter and method for driving a switch in a switching converter
A switching converter has a switch, a rectifier arrangement connected to the switch, a controller arrangement providing a control signal dependent on the output...
US-7,339,237 Connection, configuration, and production of a buried semiconductor layer
A power transistor has a semiconductor volume including a plurality of transistor cells connected in parallel, a laterally oriented, highly conductive...
US-7,339,224 Trench capacitor and corresponding method of production
The invention relates to a trench capacitor, in particular for use in a semiconductor memory cell, comprising a trench (2), embodied in a substrate (1), a first...
US-7,339,186 IC chip with nanowires
Arrangement of nanowires with PN junctions between bit lines and word lines are arranged as a ROM memory cell array. A number of the nanowires have dielectric...
US-7,338,843 Method for producing an electronic component, especially a memory chip
A method for producing an electronic component, especially a memory chip, using a laser-induced correction to equalize an integrated circuit by means of at least...
US-7,337,967 Chip card module
A chip card module having a carrier with contact areas. Arranged on the carrier lying opposite the contact areas is a semiconductor chip, which has an integrated...
US-7,337,966 Transmission interface
A data transmission method and interface for interchanging data between a reader and a chip card, wherein the data transmission interface has a variable number...
US-7,337,345 Input circuit for an electronic circuit and a method for controlling the reading-in of a data signal
The invention relates to a method for controlling the reading-in of a data signal at an input of an electrical circuit to an input latch with the aid of a clock...
US-7,337,343 Arrangement consisting of a program-controlled unit and a power chip connected to it
An arrangement including a program-controlled unit and a power chip, the power chip connected to drive electric loads in accordance with load control data, and...
US-7,337,284 Integrated semiconductor memory
An integrated semiconductor memory includes a memory cell array having memory cells for storing a datum having a first and a second data value. An input datum...
US-7,337,282 Memory system and process for controlling a memory component to achieve different kinds of memory...
According to the invention, a memory system, and a process for controlling a memory component, to achieve different kinds of memory characteristics on one and...
US-7,336,735 Viterbi decoder
Viterbi decoder for decoding a received sequence of data symbols which are coded using a predetermined coding instruction is provided. The Viterbi decoder...
US-7,336,717 Receiver circuit, in particular for a mobile radio
A radio receiver with a low intermediate frequency has a first mixer stage that can be fed with a modulated input signal and at whose output a complex...
US-7,336,625 Method and system for transmitting data via a radio interface
Transmission data are transmitted via a radio interface between an analog telephone link and a user apparatus. A base station for a cordless telephone that is...
US-7,336,552 Sense amplifier connecting/disconnecting circuit arrangement and method for operating such a circuit arrangement
An apparatus and method for operating a sense amplifier connecting/disconnecting circuit arrangement, in particular for a semiconductor memory device, including...
US-7,336,126 Subtractor circuit and power detector arrangement having that subtractor circuit
A subtractor circuit which provides, at an output, a signal that is proportional to the difference, which is applied to the input, between two signal levels is...
US-7,336,085 Current sensing circuit
A circuit arrangement for detecting a load current through a load includes a main transistor, a sensing transistor through which a load current flows that is a...
US-7,335,939 Semiconductor memory device and method of production
An array of charge-trapping memory cells and pluralities of parallel wordlines and parallel bitlines running transversely to the wordlines are arranged on a...
US-7,335,936 DRAM memory having vertically arranged selection transistors
Memory cell having a trench capacitor that is constructed in a lower region of a substantially perpendicular trench hole, and which comprises an inner and an...
US-7,335,591 Method for forming three-dimensional structures on a substrate
A method of forming a resist layer on a non-planar surface of a substrate includes placing the non-planar surface into an electrophoretic resist. While the...
US-7,335,582 Component
Semiconductor component, having a first chip arranged on a second chip, in which the first and second chips in each case have, on one of their main areas, first...
US-7,334,317 Method of forming magnetoresistive junctions in manufacturing MRAM cells
A method of forming a magnetoresistive junction in a process of manufacturing a magnetoresistive memory cell includes providing a semiconductor substrate having...
US-7,334,150 Memory module with a clock signal regeneration circuit and a register circuit for temporarily storing the...
A semiconductor memory module includes a plurality of semiconductor memory chips and bus signal lines that supply an incoming clock signal and incoming command...
US-7,333,915 Signal conditioning arrangement and method of conditioning a signal
A signal conditioning arrangement includes a sensor arrangement for sensing a measured quantity and for outputting an output signal having a first or a second...
US-7,333,577 Method for equalization of a data signal taking account of interference channels
A method for equalization of a signal is provided, wherein the equalization is of a signal that is transmitted via a data channel based on the DF method. The...
US-7,333,572 Viterbi equalization using a table memory for provision of reconstructed signal values for the calculation of...
In a method for equalization of a data signal based on the Viterbi algorithm, trellis contributions are first of all calculated for reconstructed signal values...
US-7,333,388 Multi-port memory cells
A memory array comprises memory cells of the dynamic type having a first and a second port. A cache memory is connected to the address and data paths of the...
US-7,333,383 Fuse resistance read-out circuit
Methods and apparatus for a more precise readout of fuse resistance than a conventional binary readout are provided. For some embodiments, a digital readout of...
US-7,333,382 Method and apparatus for an oscillator within a memory device
An apparatus for controlling generation of pulses for refresh operations of a memory device having a pad to transfer information and to receive signals from an...
US-7,333,358 Memory element
A memory element having a first and second logic components, each having a first input, a second input, and an output. The first input of each of the logic...
US-7,333,041 System for analog-to-digital conversion
An analog-to-digital converter system converts an analog input signal into a digital output signal. The analog input signal is converted into a first digital...
US-7,332,970 Integrated amplifier, electronic communication unit with integrated amplifier and method for operating the...
An integrated amplifier has a resonant circuit with a tuneable center frequency, in which the resonant circuit has at least one coil and at least one varactor...
US-7,332,899 Circuit arrangement for monitoring a voltage supply, and for reliable locking of signal levels when the voltage...
A circuit arrangement for monitoring an external voltage supply (VBAT1, VBAT2) and for reliable locking of a signal (Z2), which is emitted from a logic circuit...
US-7,332,812 Memory card with connecting portions for connection to an adapter
Semiconductor devices having conductive lines with extended ends and methods of extending conductive line ends by a variable distance are disclosed. An end of a...
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