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Method for carrying out a double or multiple exposure
The mutually associated structure patterns, which are provided on one mask, or a plurality of masks for a double or multiple exposure can be received by the mask...
Duty cycle corrector
A duty cycle corrector includes a first controllable delay, a second controllable delay, a phase detector, and a compensation circuit. The first controllable...
MRAM memory cell with a reference layer and method for fabricating
The invention relates to a method for fabricating a reference layer for MRAM memory cells and an MRAM memory cell equipped with a reference layer of this type. A...
Input switching arrangement for a semiconductor circuit and test method
for unidirectional input drivers in...
Transfer switching devices, which supplement unidirectional input switching arrangements or pad circuits are employed to route an internal test signal to the...
Voltage monitoring test mode and test adapter
A testing system has a processor, a module and at least one manufactured semiconductor device. The processor is configured to send and receive testing signals....
Integrated memory and method for testing the memory
An integrated memory includes command terminals for receiving command signals in a normal operation and in a test operation of the memory, and also a signal...
Method for on-demand generation of individual random numbers of a sequence
of random numbers of a 1/f noise
A method for adaptively generating a series of random numbers of a 1/f noise is based on the use of normally distributed random numbers. The method enables a...
Transmission configuration, in particular for mobile radio communication,
and mobile station with the...
A transmission configuration with a baseband module and a radio-frequency module is particularly suitable for transmission for mobile radio purposes. An...
Self test for the phase angle of the data read clock signal DQS
The invention relates to a semiconductor memory apparatus having at least one clock input contact for inputting an external clock signal, at least one clock...
Method and circuit for reading a dynamic memory circuit
A method for reading data from a dynamic memory circuit is provided, wherein at least one memory cell can be addressed via a word line and a bit line, wherein...
Integrated circuit including memory cell for storing an information item
The invention relates to a memory cell for providing an information item, having a memory element, which has a PMC resistance component with a solid electrolyte...
Integrated read-only memory, method for operating said read-only memory
and corresponding production method
An integrated read-only memory having select transistors, each of which has a drain connection and an electrode connection for feeding an electrical signal such...
Method for determining the depth of a buried structure
The present invention relates to a method for determining the depth of a buried structure in a semiconductor wafer. According to the invention, the layer...
Method for the formation of a structure size measured value
The structure size of a structure (100) is measured by forming an auxiliary measured value (Dx', Dy'). A calibration measured value (Px', Py') is determined on...
Digital-analog converter and digital-analog conversion method
The present invention provides a digital-analog converter having: a DEM logic device (10) for generating at least two digital output data items (13, 14) from the...
Test socket for an integrated circuit
A test socket for an integrated circuit, wherein the test socket has a first plurality of test points for making electrical contact with contacts of a laminate...
Final passivation scheme for integrated circuits
A semiconductor device includes a substrate with an active area. A last level interconnect capping layer is disposed over the active area. A buffer layer/crack...
Electronic device with guard ring
An electronic device includes a substrate, an insulating layer arranged on the substrate, the insulating layer having an opening in an area of the surface of the...
Semiconductor device with temperature sensor
A semiconductor device is disclosed. In one embodiment the semiconductor device includes a semiconductor body of which is integrated a temperature sensor for...
Method for processing a thin semiconductor substrate
A method for processing a semiconductor substrate less than 200 .mu.m thick has been provided. The substrate has one or a plurality of semiconductor elements,...
Integrated circuit in a maximum input/output configuration
A memory includes input/output paths and electrical leads. Each of the input/output paths are coupled to separate electrical leads. The memory is configured to...
Memory system for network broadcasting applications and method for
operating the same
A memory system for network broadcasting applications, such as video/audio applications, has at least one memory which is divided into a plurality of addressable...
Programme-controlled unit with crossbar employing a diagnostic port
A programme-controlled unit comprises a crossbar with a multiplicity of ports, a multiplicity of devices which are connected to the ports of the crossbar and can...
Method and device for digital filtering of interpolated values
In the digital filtering of an input signal (3), which has been produced by interpolation of a pilot signal (2), under certain circumstances numerous values...
Transmitting and receiving arrangement with interference signal
A transmitting and receiving arrangement is disclosed having a transmission path, a reception path, and a control device for suppression of interference signals...
Method and device for the clocked output of asynchronously received
A method and device for the uniform output of asynchronously transmitted digital values is provided, including: receiving the digital values in a receiver from a...
Control unit for deactivating and activating the control signals
A control unit is set up to generate and output periodic clock signals, that are in sync with and at the same frequency as a periodic basic clock that is input...
Integrated semiconductor memory
An integrated semiconductor memory includes programmable elements, which are arranged in a continuous region on a chip area of the integrated semiconductor...
Non-volatile memory element capable of storing irreversible complementary
A non-volatile memory element for storing at least one data item, having a readable memory cell which can be written on with a first part of a data item, the...
Method for dynamically monitoring a reticle
The method of dynamically monitoring a reticle includes preventively macro monitoring and defect inspecting with regard to mechanical loading, including particle...
Method for purging an optical lens
By a unit for determining fractions of a substance in a gas or gas mixture, measurements are carried out on the gas or gas mixture for purging a lens in a...
Shared amplifier circuit
A circuit has a first amplifier having first positive and negative inputs and a second amplifier having second positive and negative inputs. A first unit is...
Control loop filter
A feedback control loop having a filter response and a cut-off frequency comprises a system under control for generating an output signal being an output signal...
Amplifier arrangement, and method for compensating for an offset
An amplifier arrangement and a method for compensating for an offset in an amplifier is provided. A respective switch for connecting together the inputs in a...
A level converter is disclosed. In one embodiment, the level converter includes a first and second input for applying a first voltage and first and second output...
Data latch, master/slave flipflop and frequency divider circuit
A data latch contains a supply connection, a reference ground potential connection and a data input. The input side of an inverter is connected to the data...
Duty cycle corrector
A duty cycle corrector, including a first, second circuit and a third circuit is disclosed. The third circuit is configured to obtain a threshold value in...
Device to be used in the synchronization of clock pulses, as well as a
clock pulse synchronization process
The invention involves a clock pulse synchronization process as well as a device to be used in the synchronization of clock pulses, including a first delay...
Pseudodynamic off-chip driver calibration
A driver system, a driver calibration circuit arrangement for calibration of an impedance of a driver circuit arrangement, and a method for calibration of an...
Power semiconductor component with increased robustness
The invention relates to a power semiconductor component with increased robustness, in which a contact layer (13, 14) applied directly to a main surface (7, 11)...
Semiconductor memory cell and associated fabrication method
A semiconductor memory cell and an associated fabrication method are provided in which a storage capacitor is connected to a selection transistor. The storage...
Method of fabricating dielectric mixed layers and capacitive element and
The present invention provides a method for fabricating a capacitive element (100), a substrate (101) being provided as a first electrode layer of the capacitive...
Method for producing a junction region between a trench and a
semiconductor zone surrounding the trench
A method for producing a junction region (2, 5, 6, 7) between a trench (3) and a semiconductor zone (2) surrounding the trench (3) in a trench semiconductor...
Semiconductor component having at least one organic semiconductor layer
and method for fabricating the same
A semiconductor component has at least one organic semiconductor layer. The component also includes at least one protective layer for at least partially covering...
Integrated memory having a test circuit for functional testing of the
An integrated memory having a plurality of memory banks includes a test circuit for functional testing of the memory. A plurality of secondary sense amplifiers...
Concept for compensating piezo-influences on an integrated semiconductor
A compensation signal, which derives the mechanical stress, which acts on an integrated semiconductor circuit, from two partial compensation signals, which are...
Method for the detection of impedances and for the qualification of the
The invention relates to a method for detection of impedances, in particular along inductances, in telephone lines of the type with two metal wires as signal...
Memory cell array
A memory cell array is formed by providing a plurality of memory cells along a substrate, where each of the memory cells includes a storage element and an access...
Electronic chip and electronic chip assembly
A multiplicity of nanotubes are applied to at least one external chip metal contact of an electronic chip in order to make contact between the electronic chip...
Voltage-controlled oscillator circuit with analogue and digital actuation
A VCO circuit (20) has a coil (21) and, in parallel therewith, a constant capacitance (24) and adjustable capacitance elements (22, 23). A first capacitance...