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Patent # Description
US-7,312,533 Electronic component with flexible contacting pads and method for producing the electronic component
An electronic component has an electronic circuit and a rubber-elastic elevation. The rubber-elastic elevation is formed of an insulating rubber-elastic material...
US-7,312,492 Method for fabricating a DRAM memory cell arrangement having fin field effect transistors and DRAM memory cell
The invention relates to the fabrication of DRAM memory cell arrangements having fin field effect transistors and curved channel field effect transistors. The...
US-7,312,491 Charge trapping semiconductor memory element with improved trapping dielectric
A semiconductor memory element, which can be controlled via field effect, includes a semiconductor substrate of a first conduction type, a first doping region of...
US-7,312,137 Transistor with shallow germanium implantation region in channel
A transistor and a structure thereof, wherein a very shallow region having a high dopant concentration of germanium is implanted into a channel region of a...
US-7,312,126 Process for producing a layer arrangement, and layer arrangement for use as a dual gate field-effect transistor
The invention relates to a process for producing a layer arrangement, in which, a porous silicon layer is formed as sacrificial layer on an auxiliary substrate,...
US-7,312,115 Fabrication method for a semiconductor structure having integrated capacitors
The present invention provides a fabrication method for a semiconductor structure having integrated capacitors and a corresponding semiconductor structure. The...
US-7,312,114 Manufacturing method for a trench capacitor having an isolation collar electrically connected with a substrate...
The present invention relates to a manufacturing method for a trench capacitor having an isolation collar which is electrically connected with a substrate on a...
US-7,311,081 Electronic throttle control system with integrated controller and power stage
One embodiment includes an apparatus comprising a closed loop feedback controller and a power output stage to couple to the closed loop feedback controller. The...
US-7,310,861 Method of producing a piezoelectric component
A method for producing a piezoelectric component comprising at least two stacked crystal filters comprises the steps of depositing of the layer stack above the...
US-7,310,791 Method for correcting layout errors
A method for correcting layout errors of a layout, for example layout errors of a layout of an electronic circuit, is disclosed. In order to be able to correct...
US-7,310,593 Sampling apparatus and method for determining the driving state of a vehicle
An apparatus for determining a state parameter of an object to be monitored comprises a means for providing a plurality of measurement values, wherein the...
US-7,310,395 Method and apparatus for correlative estimation of a mobile radio channel
In a method for correlative estimation of a mobile radio channel on the basis of a training sequence (TS) which is transmitted via the mobile radio channel, a...
US-7,310,129 Method for carrying out a double or multiple exposure
The mutually associated structure patterns, which are provided on one mask, or a plurality of masks for a double or multiple exposure can be received by the mask...
US-7,310,010 Duty cycle corrector
A duty cycle corrector includes a first controllable delay, a second controllable delay, a phase detector, and a compensation circuit. The first controllable...
US-7,309,617 MRAM memory cell with a reference layer and method for fabricating
The invention relates to a method for fabricating a reference layer for MRAM memory cells and an MRAM memory cell equipped with a reference layer of this type. A...
US-7,308,628 Input switching arrangement for a semiconductor circuit and test method for unidirectional input drivers in...
Transfer switching devices, which supplement unidirectional input switching arrangements or pad circuits are employed to route an internal test signal to the...
US-7,308,624 Voltage monitoring test mode and test adapter
A testing system has a processor, a module and at least one manufactured semiconductor device. The processor is configured to send and receive testing signals....
US-7,308,622 Integrated memory and method for testing the memory
An integrated memory includes command terminals for receiving command signals in a normal operation and in a test operation of the memory, and also a signal...
US-7,308,467 Method for on-demand generation of individual random numbers of a sequence of random numbers of a 1/f noise
A method for adaptively generating a series of random numbers of a 1/f noise is based on the use of normally distributed random numbers. The method enables a...
US-7,308,038 Transmission configuration, in particular for mobile radio communication, and mobile station with the...
A transmission configuration with a baseband module and a radio-frequency module is particularly suitable for transmission for mobile radio purposes. An...
US-7,307,895 Self test for the phase angle of the data read clock signal DQS
The invention relates to a semiconductor memory apparatus having at least one clock input contact for inputting an external clock signal, at least one clock...
US-7,307,869 Method and circuit for reading a dynamic memory circuit
A method for reading data from a dynamic memory circuit is provided, wherein at least one memory cell can be addressed via a word line and a bit line, wherein...
US-7,307,868 Integrated circuit including memory cell for storing an information item and method
The invention relates to a memory cell for providing an information item, having a memory element, which has a PMC resistance component with a solid electrolyte...
US-7,307,865 Integrated read-only memory, method for operating said read-only memory and corresponding production method
An integrated read-only memory having select transistors, each of which has a drain connection and an electrode connection for feeding an electrical signal such...
US-7,307,735 Method for determining the depth of a buried structure
The present invention relates to a method for determining the depth of a buried structure in a semiconductor wafer. According to the invention, the layer...
US-7,307,715 Method for the formation of a structure size measured value
The structure size of a structure (100) is measured by forming an auxiliary measured value (Dx', Dy'). A calibration measured value (Px', Py') is determined on...
US-7,307,567 Digital-analog converter and digital-analog conversion method
The present invention provides a digital-analog converter having: a DEM logic device (10) for generating at least two digital output data items (13, 14) from the...
US-7,307,443 Test socket for an integrated circuit
A test socket for an integrated circuit, wherein the test socket has a first plurality of test points for making electrical contact with contacts of a laminate...
US-7,307,346 Final passivation scheme for integrated circuits
A semiconductor device includes a substrate with an active area. A last level interconnect capping layer is disposed over the active area. A buffer layer/crack...
US-7,307,329 Electronic device with guard ring
An electronic device includes a substrate, an insulating layer arranged on the substrate, the insulating layer having an opening in an area of the surface of the...
US-7,307,328 Semiconductor device with temperature sensor
A semiconductor device is disclosed. In one embodiment the semiconductor device includes a semiconductor body of which is integrated a temperature sensor for...
US-7,307,010 Method for processing a thin semiconductor substrate
A method for processing a semiconductor substrate less than 200 .mu.m thick has been provided. The substrate has one or a plurality of semiconductor elements,...
US-7,305,594 Integrated circuit in a maximum input/output configuration
A memory includes input/output paths and electrical leads. Each of the input/output paths are coupled to separate electrical leads. The memory is configured to...
US-7,305,525 Memory system for network broadcasting applications and method for operating the same
A memory system for network broadcasting applications, such as video/audio applications, has at least one memory which is divided into a plurality of addressable...
US-7,305,512 Programme-controlled unit with crossbar employing a diagnostic port
A programme-controlled unit comprises a crossbar with a multiplicity of ports, a multiplicity of devices which are connected to the ports of the crossbar and can...
US-7,305,425 Method and device for digital filtering of interpolated values
In the digital filtering of an input signal (3), which has been produced by interpolation of a pilot signal (2), under certain circumstances numerous values...
US-7,305,216 Transmitting and receiving arrangement with interference signal suppression control
A transmitting and receiving arrangement is disclosed having a transmission path, a reception path, and a control device for suppression of interference signals...
US-7,305,059 Method and device for the clocked output of asynchronously received digital signals
A method and device for the uniform output of asynchronously transmitted digital values is provided, including: receiving the digital values in a receiver from a...
US-7,304,909 Control unit for deactivating and activating the control signals
A control unit is set up to generate and output periodic clock signals, that are in sync with and at the same frequency as a periodic basic clock that is input...
US-7,304,899 Integrated semiconductor memory
An integrated semiconductor memory includes programmable elements, which are arranged in a continuous region on a chip area of the integrated semiconductor...
US-7,304,879 Non-volatile memory element capable of storing irreversible complementary data
A non-volatile memory element for storing at least one data item, having a readable memory cell which can be written on with a first part of a data item, the...
US-7,304,721 Method for dynamically monitoring a reticle
The method of dynamically monitoring a reticle includes preventively macro monitoring and defect inspecting with regard to mechanical loading, including particle...
US-7,304,716 Method for purging an optical lens
By a unit for determining fractions of a substance in a gas or gas mixture, measurements are carried out on the gas or gas mixture for purging a lens in a...
US-7,304,598 Shared amplifier circuit
A circuit has a first amplifier having first positive and negative inputs and a second amplifier having second positive and negative inputs. A first unit is...
US-7,304,546 Control loop filter
A feedback control loop having a filter response and a cut-off frequency comprises a system under control for generating an output signal being an output signal...
US-7,304,534 Amplifier arrangement, and method for compensating for an offset
An amplifier arrangement and a method for compensating for an offset in an amplifier is provided. A respective switch for connecting together the inputs in a...
US-7,304,525 Level converter
A level converter is disclosed. In one embodiment, the level converter includes a first and second input for applying a first voltage and first and second output...
US-7,304,519 Data latch, master/slave flipflop and frequency divider circuit
A data latch contains a supply connection, a reference ground potential connection and a data input. The input side of an inverter is connected to the data...
US-7,304,517 Duty cycle corrector
A duty cycle corrector, including a first, second circuit and a third circuit is disclosed. The third circuit is configured to obtain a threshold value in...
US-7,304,515 Device to be used in the synchronization of clock pulses, as well as a clock pulse synchronization process
The invention involves a clock pulse synchronization process as well as a device to be used in the synchronization of clock pulses, including a first delay...
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