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Patent # Description
US-7,376,802 Memory arrangement
The present invention relates to a memory arrangement having a controller and having at least one memory device. Data signals, control signals and address...
US-7,376,689 Method and apparatus for reducing the crest factor of a signal
A method and apparatus for reducing the crest factor of a signal uses a plurality of partial correction signals having respective predetermined frequencies. For...
US-7,376,512 Method for determining an optimal absorber stack geometry of a lithographic reflection mask
The present invention relates to a method for determining an optimal absorber stack geometry of a lithographic reflection mask comprising a reflection layer and...
US-7,376,117 Interleaving circuit for a multiband OFDM transceiver
Interleaving circuit for a multiband OFDM (orthogonal frequency division multiplexing) transceiver of a ultra wide band wireless personal access network...
US-7,376,026 Integrated semiconductor memory having sense amplifiers selectively activated at different timing
An integrated semiconductor memory includes a memory cell array in which first sense amplifiers are arranged on a right-hand side of the memory cell array and...
US-7,376,018 Non-volatile memory device with single transistor memory cell
A non-volatile memory device includes a plurality of word lines, a plurality of sense lines, and a plurality of non-volatile memory cells. Each memory cell...
US-7,375,999 Low equalized sense-amp for twin cell DRAMs
Embodiments of the invention provide a method and apparatus for accessing a twin cell memory device. In one embodiment, a twin memory cell is accessed using a...
US-7,375,983 Circuit board for reducing crosstalk of signals
A circuit board includes a first group of layers located close to a top side of the circuit board, and a second group of layers located close to an underside of...
US-7,375,971 Memory module with an electronic printed circuit board and a plurality of semiconductor chips of the same type
In a first embodiment, the invention provides a memory module having an electronic printed circuit board and a plurality of semiconductor chips of the same type...
US-7,375,576 Log circuit and highly linear differential-amplifier circuit
A log circuit receives an operated current signal and a reference current signal at respective inputs and comprises an operand log circuit including a first...
US-7,375,508 Device and a process for the calibration of a semiconductor component test system
A device and a process for the calibration of a semi-conductor component test systemThe invention relates to a process and a device for the calibration of a...
US-7,375,434 Semiconductor chip with flexible contacts at a face
The present invention relates to a semiconductor chip comprising a semiconductor element, at least a conducting line and a contact area being arranged on the...
US-7,375,395 Vertical field-effect transistor in source-down structure
The invention relates to a vertical field-effect transistor in source-down structure, in which the active zones (10, 7, 11) are introduced from trenches (5, 8,...
US-7,375,387 Method for producing semiconductor memory devices and integrated memory device
The invention provides an integration scheme for a memory cell array, especially a charge-trapping memory cell array, comprising an architecture of local...
US-7,375,029 Method for fabricating contact holes in a semiconductor body and a semiconductor structure
A method for fabricating contact holes in a semiconductor body proceeds from a structure in which: a plurality of trenches isolated from one another by mesa...
US-7,374,952 Methods of patterning a magnetic stack of a magnetic memory cell and structures thereof
Methods of patterning a magnetic stack of a magnetic memory cell and structures thereof. At least the top magnetic material layer of a magnetic stack is...
US-7,373,583 ECC flag for testing on-chip error correction circuit
The present invention includes an error correction circuit with a data memory, a control circuit, a parity memory, and a recorder. The data memory is configured...
US-7,373,562 Memory circuit comprising redundant memory areas
The invention relates to a memory circuit comprising regular memory areas and redundant memory areas, redundancy circuits in each case being assigned to the...
US-7,373,445 Method and apparatus for allocating bus access rights in multimaster bus systems
A method for allocating bus access rights is used in a multimaster bus system wherein addresses are explicitly allocated to master devices and each master device...
US-7,372,923 Method for equalization of a payload signal, taking into account an interference source
In a method for equalization of a signal which is transmitted via a payload channel taking into account at least one interference channel, the trellis diagram...
US-7,372,918 Transmission device with adaptive digital predistortion, transceiver with transmission device, and method for...
The invention provides a transmission device having adaptive digital predistortion, which has a transmission path and a feedback path. The transmission path...
US-7,372,750 Integrated memory circuit and method for repairing a single bit error
The invention relates to an integrated memory circuit having a memory cell array comprising memory cells arranged on word lines and bit lines, and having a...
US-7,372,749 Methods for repairing and for operating a memory component
In a method for repairing a memory component, data retention times of regular memory cells are determined. Weak regular memory cells having a data retention time...
US-7,372,725 Integrated circuit having resistive memory
A memory device including a memory cell, a first circuit, and a second circuit. The memory cell includes phase-change material. The first circuit is configured...
US-7,372,716 Memory having CBRAM memory cells and method
A memory cell arrangement has a plurality of memory cells of the CBRAM type and a programming apparatus, the memory cells being arranged along bit lines and each...
US-7,372,579 Apparatus and method for monitoring trench profiles and for spectrometrologic analysis
An apparatus for monitoring a trench profile of a substrate includes a radiation-emitting unit for irradiating the substrate with infrared radiation. The...
US-7,372,383 Method for calibrating a digital/analog converter and digital/analog converter
A digital/analog converter comprises a converter array comprised of a plurality of converter cells and a device for self-calibration of the converter cells. The...
US-7,372,343 Oscillator circuit
The invention is directed to an oscillator circuit in which a frequency-determining resonant circuit includes an inductive element, a first capacitive element...
US-7,372,334 Output match transistor
A power transistor, having: a semiconductor having an electrode formed thereon, wherein the electrode comprises a plurality of interdigitated transistors each...
US-7,372,331 Receiver circuit
A receiver circuit for receiving and forwarding data signals comprises at least one first and one second input to be used to inject an external digital data...
US-7,372,103 MOS field plate trench transistor device
A MOS field plate trench transistor device is disclosed. In one embodiment, in order to obtain a lowest possible on resistance, in the case of a MOS field plate...
US-7,372,095 Integrated semiconductor circuit comprising a transistor and a strip conductor
An integrated semiconductor circuit includes a transistor and a strip conductor (11). The transistor includes a first (1) and a second source/drain region (2)...
US-7,372,093 DRAM memory with vertically arranged selection transistors
The invention relates to a semiconductor memory, particularly a DRAM, in which the memory cells in each case have a trench capacitor arranged in a lower area of...
US-7,372,072 Semiconductor wafer with test structure
The invention relates to a semiconductor wafer (1) having a plurality of first sawing regions (201-211) running parallel to one another in a first direction (X)...
US-7,371,657 Method for forming an isolating trench with a dielectric material
The present invention relates to a method of forming an isolating trench of a semiconductor device with a dielectric material, and to a method of forming an...
US-7,371,650 Method for producing a transistor structure
A method for fabricating a transistor structure with a first and a second bipolar transistor having different collector widths is presented. The method includes...
US-7,371,645 Method of manufacturing a field effect transistor device with recessed channel and corner gate device
Fabrication of recessed channel array transistors (RCAT) with a corner gate device includes forming pockets between a semiconductor fin that includes a gate...
US-7,371,012 Optoelectronic module and plug arrangement
A compact optoelectronic module that prevents undesirable heating by locating the electrical drive and/or receiving (control) circuit outside of the housing...
US-7,370,313 Method for optimizing a photolithographic mask
The invention relates to a method for optimizing a mask layout pattern comprising at least one structural feature. First a desired layout pattern is provided....
US-7,370,303 Method for determining the arrangement of contact areas on the active top side of a semiconductor chip
In the case of a method according to the invention for determining the arrangement of contact areas on the active top side of a semiconductor chip arranged in or...
US-7,369,969 Holding device for a sensor signal, method for forwarding a sensor signal and computer program
A holding device for a sensor signal comprises a signal input receiving a sensor signal, a signal output and a storage device coupled to the signal input and...
US-7,369,602 Adaptive channel estimation by means of variation of the integration length during the despreading of...
In the method, the received spread-coded signal sequence r.sub.k(i) is first of all correlated with the spread-coded training symbol sequence in a correlator...
US-7,369,568 ATM-port with integrated ethernet switch interface
An ATM-port module for an ATM-node having an Ethernet switch includes an ATM-controller; and an Ethernet-switch interface connecting it to the Ethernet switch....
US-7,369,426 Magnetoresistive memory cell with dynamic reference layer
The present invention relates to an arrangement for increasing a relative change in resistance of a magnetoresistive memory cell (17) having in each case a...
US-7,369,382 Integrated circuit with an undervoltage detector
An integrated circuit arrangement includes connection terminals, an undervoltage detector, and at least one circuit unit. The connection terminals are configured...
US-7,368,948 Integrated receiver circuit
An integrated receiver circuit for amplifying an input signal based on a reference signal includes two voltage converters to respectively convert the input and...
US-7,368,833 Multichannel DC/DC converter
An apparatus which has a first stage with an input circuit with an inductive element (1), a second stage with a number of output circuits with loads (3, 4, 5)...
US-7,368,824 Diffusion solder position, and process for producing it
A diffusion solder position between two parts has intermetallic phases formed by two solder components. Nanoparticles of a filler material are ...
US-7,368,804 Method and apparatus of stress relief in semiconductor structures
A method, apparatus and system are provided for relieving stress in the via structures of semiconductor structures whenever a linewidth below a via is larger...
US-7,368,752 DRAM memory cell
A DRAM memory cell is provided with a selection transistor, which is arranged horizontally at a semiconductor substrate surface and has a first source/drain...
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