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Fabrication method for a trench capacitor having an insulation collar
The present invention provides a fabrication method for a trench capacitor having an insulation collar (10) in a silicon substrate (1), having the steps of:...
Method for producing an annular microstructure element
An annular microstructure element, in particular an annularly arranged monolayer or multilayer thin film, is formed over a substrate (S), e.g., for use in a...
Integrated circuit arrangement with intermediate materials and associated
An integrated circuit arrangement having a metallization layer, an interconnect dielectric, electrically conductive interconnect intermediate material,...
Memory module with a test device
A memory module, which enables a module-internal, cross-chip electrical functional test of a plurality of integrated memory chips arranged on a printed circuit...
Adaptive searcher threshold setting using consecutive ISCP measurements
Dynamic adjustment of searcher thresholds used to detect propagation paths of a communications signal transmitted from a transmitter to the base band receiver....
Hybrid memory cell for spin-polarized electron current induced switching
and writing/reading process using such...
The present invention relates to a magnetoresistive hybrid memory cell comprising a first stacked structure comprising a magnetic tunnel junction including first...
Semiconductor memory module
A semiconductor memory module includes an electronic printed circuit board with a contact strip and a plurality of semiconductor memory chips of identical type...
The invention relates to an analog-to-digital converter. The analog-to-digital converter, for conversion of a signal for digitization into a digital signal,...
Method for producing a semiconductor structure
In a method for producing a semiconductor structure a semiconductor a substrate with a top surface is provided. A gate dielectric layer is provided on the top...
Integrated semiconductor memory
An integrated semiconductor memory includes memory cells that store a first data record has at least one datum with a first or second data value and a second...
Memory arrangement in a computer system
A memory arrangement in a computer system can have at least one memory module with semiconductor components, which are arranged on the memory module, can be...
Device and method for testing an electrical circuit
A method and device for testing an electrical circuit, which do not require a thorough electrical circuit simulation but reliably identifying circuit faults....
Low-latency DC compensation
A method of performing DC estimation and correction in the presence of an automatic gain control function introduces no long-term delay of the signal. When the...
Method and apparatus for phase detection
The present invention relates to a method and apparatus for generating an output signal in dependence on a phase difference between two periodic signals. The...
Method and device for transmitting and identifying a modulation type in
digital communication systems by way of...
Data symbols in the training sequence are rotated at the transmitter end through a phase rotation factor which is specific for a given modulation type that is...
Apparatus for data transmission path detection
A method and apparatus for detecting paths of a received signal by analyzing a delay power profile of the received signal comprises a detection of peaks in the...
Apparatus and method for calculating and implementing a Fibonacci mask for
a code generator
An apparatus and method for calculating and implementing a Fibonacci mask for a code generator is disclosed herein. The first step receives a desired code offset...
Network device and its data transmission method
A network device for transmitting data of a host system to a network including a buffer for storing the data, a first transmission interface providing a control...
Integrated semiconductor memory with temperature-dependent voltage
An integrated semiconductor memory device includes a temperature sensor circuit to generate a temperature-dependent control signal, a reference circuit to...
Magnetic Memory Array
A magnetic memory is disclosed. In one embodiment, the magnetic memory array includes a plurality of cell columns and a pair of reference cell columns, including...
Random access memory including first and second voltage sources
A random access memory including first memory cells, second memory cells, a first voltage source, and a second voltage source. The first voltage source is...
Devices and methods for calibrating amplifier stages and for compensating
for errors in amplifier stages of...
Devices and methods for calibration of amplifier stages and for compensation of errors in components connected upstream of amplifier stagesThe described...
Voltage regulation system
A voltage regulation process, as well as a voltage regulation system, are discussed. A first voltage present at an input of the voltage regulation system is...
Actuation circuit for a switch in a switch-mode converter for improving
the response to sudden changes
An actuation circuit is provided for a switch controlling the power consumption in a switch-mode converter which has input terminals for applying an input...
Electronic component with flexible contacting pads and method for
producing the electronic component
An electronic component has an electronic circuit and a rubber-elastic elevation. The rubber-elastic elevation is formed of an insulating rubber-elastic material...
Method for fabricating a DRAM memory cell arrangement having fin field
effect transistors and DRAM memory cell
The invention relates to the fabrication of DRAM memory cell arrangements having fin field effect transistors and curved channel field effect transistors. The...
Charge trapping semiconductor memory element with improved trapping
A semiconductor memory element, which can be controlled via field effect, includes a semiconductor substrate of a first conduction type, a first doping region of...
Transistor with shallow germanium implantation region in channel
A transistor and a structure thereof, wherein a very shallow region having a high dopant concentration of germanium is implanted into a channel region of a...
Process for producing a layer arrangement, and layer arrangement for use
as a dual gate field-effect transistor
The invention relates to a process for producing a layer arrangement, in which, a porous silicon layer is formed as sacrificial layer on an auxiliary substrate,...
Fabrication method for a semiconductor structure having integrated
The present invention provides a fabrication method for a semiconductor structure having integrated capacitors and a corresponding semiconductor structure. The...
Manufacturing method for a trench capacitor having an isolation collar
electrically connected with a substrate...
The present invention relates to a manufacturing method for a trench capacitor having an isolation collar which is electrically connected with a substrate on a...
Electronic throttle control system with integrated controller and power
One embodiment includes an apparatus comprising a closed loop feedback controller and a power output stage to couple to the closed loop feedback controller. The...
Method of producing a piezoelectric component
A method for producing a piezoelectric component comprising at least two stacked crystal filters comprises the steps of depositing of the layer stack above the...
Method for correcting layout errors
A method for correcting layout errors of a layout, for example layout errors of a layout of an electronic circuit, is disclosed. In order to be able to correct...
Sampling apparatus and method for determining the driving state of a
An apparatus for determining a state parameter of an object to be monitored comprises a means for providing a plurality of measurement values, wherein the...
Method and apparatus for correlative estimation of a mobile radio channel
In a method for correlative estimation of a mobile radio channel on the basis of a training sequence (TS) which is transmitted via the mobile radio channel, a...
Method for carrying out a double or multiple exposure
The mutually associated structure patterns, which are provided on one mask, or a plurality of masks for a double or multiple exposure can be received by the mask...
Duty cycle corrector
A duty cycle corrector includes a first controllable delay, a second controllable delay, a phase detector, and a compensation circuit. The first controllable...
MRAM memory cell with a reference layer and method for fabricating
The invention relates to a method for fabricating a reference layer for MRAM memory cells and an MRAM memory cell equipped with a reference layer of this type. A...
Input switching arrangement for a semiconductor circuit and test method
for unidirectional input drivers in...
Transfer switching devices, which supplement unidirectional input switching arrangements or pad circuits are employed to route an internal test signal to the...
Voltage monitoring test mode and test adapter
A testing system has a processor, a module and at least one manufactured semiconductor device. The processor is configured to send and receive testing signals....
Integrated memory and method for testing the memory
An integrated memory includes command terminals for receiving command signals in a normal operation and in a test operation of the memory, and also a signal...
Method for on-demand generation of individual random numbers of a sequence
of random numbers of a 1/f noise
A method for adaptively generating a series of random numbers of a 1/f noise is based on the use of normally distributed random numbers. The method enables a...
Transmission configuration, in particular for mobile radio communication,
and mobile station with the...
A transmission configuration with a baseband module and a radio-frequency module is particularly suitable for transmission for mobile radio purposes. An...
Self test for the phase angle of the data read clock signal DQS
The invention relates to a semiconductor memory apparatus having at least one clock input contact for inputting an external clock signal, at least one clock...
Method and circuit for reading a dynamic memory circuit
A method for reading data from a dynamic memory circuit is provided, wherein at least one memory cell can be addressed via a word line and a bit line, wherein...
Integrated circuit including memory cell for storing an information item
The invention relates to a memory cell for providing an information item, having a memory element, which has a PMC resistance component with a solid electrolyte...
Integrated read-only memory, method for operating said read-only memory
and corresponding production method
An integrated read-only memory having select transistors, each of which has a drain connection and an electrode connection for feeding an electrical signal such...
Method for determining the depth of a buried structure
The present invention relates to a method for determining the depth of a buried structure in a semiconductor wafer. According to the invention, the layer...
Method for the formation of a structure size measured value
The structure size of a structure (100) is measured by forming an auxiliary measured value (Dx', Dy'). A calibration measured value (Px', Py') is determined on...