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Patent # Description
US-7,365,402 LDMOS transistor
An LDMOS semiconductor transistor structure comprises a substrate having an epitaxial layer of a first conductivity type, a source region extending from a...
US-7,365,382 Semiconductor memory having charge trapping memory cells and fabrication method thereof
A semiconductor memory having charge trapping memory cells, where the direction of current flow of each channel region of the memory transistors runs...
US-7,365,025 Methods of forming dual-damascene interconnect structures on semiconductor substrates using multiple...
Methods of forming integrated circuit devices include patterning an electrically insulating layer to support dual-damascene interconnect structures therein. The...
US-7,364,999 Method for interconnecting semiconductor components with substrates and contact means
A semiconductor component includes a substrate having a plurality of compliant contact bumps formed over a surface thereof. A semiconductor chip has a plurality...
US-7,364,975 Semiconductor device fabrication methods
Methods of fabricating semiconductor devices are disclosed. In a preferred embodiment, a method of fabricating a semiconductor device includes providing a...
US-RE40,275 Method for producing a memory cell
A method for producing a memory cell includes masking a desired polysilicon structure with an oxidation-inhibiting layer, preferably a nitride layer. The...
US-7,363,602 Computer-supported, automated method for the verification of analog circuits
The invention relates to a computer-supported, automated method for the verification of analog circuits, and to a storage medium on which a computer software...
US-7,363,561 Method and circuit arrangement for resetting an integrated circuit
The invention relates to a method for resetting at least one circuit part of an integrated circuit, in particular a synchronous semiconductor memory, in which a...
US-7,362,998 Mobile military satellite receiver architecture for accommodating wide carrier offset and method of performing...
A coarse carrier offset adapter for determining a coarse carrier offset for application to a received satellite signal, a method of performing coarse carrier...
US-7,362,798 Method for transmitting data to be transmitted using a subscriber modem
A method transmits data to be transmitted using a subscriber modem of a subscriber access network with adjusted transmission power. The method includes selecting...
US-7,362,650 Memory arrangement having a plurality of RAM chips
Embodiments of the invention provide a memory arrangement having an even number k=4 of physically spaced RAM chips, on each of which it is possible for m data...
US-7,362,633 Parallel read for front end compression mode
Methods and apparatus for increasing front-end testing throughput by allowing simultaneous access to multiple banks are provided. Techniques described herein...
US-7,362,632 Test parallelism increase by tester controllable switching of chip select groups
Embodiments of the invention generally provide methods and systems for increasing the level of parallelism in testing memory devices. A set of test signals...
US-7,362,622 System for determining a reference level and evaluating a signal on the basis of the reference level
A circuit exhibits a signal input, means for determining a reference level on the basis of properties of a signal received at the signal input. In addition, the...
US-7,362,608 Phase change memory fabricated using self-aligned processing
A memory includes transistors in rows and columns providing an array, first conductive lines in columns across the array, and second conductive lines...
US-7,362,453 Method for the characterization of a film
A method for the characterization of a film arranged in a plurality of regions on a substrate forms a respective optical measurement at each of a multiplicity of...
US-7,362,264 Interference management
A GPS system is configured to manage interference from disturbing signals. The system includes an antenna, an RF front end unit, a filtering unit, amplifying...
US-7,362,157 Circuit arrangement with a transistor having a reduced reverse current
A circuit arrangement is disclosed herein having an input terminal configured to receive an input voltage, and an output terminal to provide an output voltage...
US-7,361,974 Manufacturing method for an integrated semiconductor structure
The present invention provides a manufacturing method for an integrated semiconductor structure comprising the steps of: providing a semiconductor substrate...
US-7,361,970 Method for production of a buried stop zone in a semiconductor component and semiconductor component comprising...
A method for the production of a stop zone in a doped zone of a semiconductor body having a first side and a second side, comprises the following method steps: ...
US-7,361,925 Integrated circuit having a memory including a low-k dielectric material for thermal isolation
The present invention includes a memory cell device and method that includes a memory cell, a first electrode, a second electrode, phase-change material and an...
US-7,361,924 Non-volatile memory element and production method thereof and storage memory arrangement
A nonvolatile memory element and associated production methods and memory element arrangements are presented. The nonvolatile memory element has a changeover...
US-7,361,549 Method for fabricating memory cells for a memory device
The invention provides a method for fabricating a memory device having memory cells which are formed on a microstructured driving unit (100), in which method a...
US-7,361,538 Transistors and methods of manufacture thereof
Transistors and methods of manufacture thereof are disclosed. A workpiece is provided, a gate dielectric is formed over the workpiece, and a gate is formed over...
US-7,361,434 Phase shift mask
Semitransparent and trenchlike, absorber-free structure elements are formed jointly on a photomask formed using phase mask technology. The trenchlike structure...
US-7,360,203 Program tracing in a multithreaded processor
A multithreaded processor includes a thread ID for each set of fetched bits in an instruction fetch and issue unit. The thread ID attaches to the instructions...
US-7,360,139 Semiconductor component, arrangement and method for characterizing a tester for semiconductor components
A tester for semiconductor components with a plurality of channels is connected to a specific semiconductor component in order to characterize the signal path...
US-7,360,036 Data memory circuit
A data memory circuit is provided. In one embodiment, the data memory circuit comprises a plurality of addressable memory cells, a command decoding device for...
US-7,359,443 Method for compensating for peak values during a data transmission with discrete multitone symbols and a...
The invention provides a method for transmitting an analog data stream (101) from a data stream transmitter (214) to a data stream receiver (215) by means of...
US-7,359,435 Method of evaluation of a bit error rate measurement for indication of a channel quality
In a method for efficient evaluation of measurement values from a bit error rate measurement for indication of channel quality, the characteristic of the...
US-7,359,278 Method for producing an integrated memory module
A method for producing an integrated memory module containing a command decoding device that responds to external operation commands to set operating states of...
US-7,359,271 Gate induced drain leakage current reduction by voltage regulation of master wordline
A semiconductor integrated circuit device and method for reducing gate induced leakage current associated with circuits of the semiconductor electrical device,...
US-7,359,259 Method for transmission and reception of a data signal on a line pair, as well as a transmission and reception...
Apparatuses and methods for transmitting and receiving a data signal on a line pair having a first transmission line and a second transmission line are provided....
US-7,359,257 Semiconductor memory module and electronic apparatus including a semiconductor memory module and method for...
A semiconductor memory module (1) includes a circuit substrate (2), a first (100), a second (200), a third (300) and a fourth (400) rank of memory chips (3), a...
US-7,359,252 Memory data bus structure and method of transferring information with plural memory banks
A data bus structure for a dynamic random access memory (DRAM) according to the present invention includes a series of data buses, each shared by a plurality of...
US-7,359,232 Multi-context memory cell
The multi-context memory cell comprises a first memory means for storing an item of data information and also a plurality of second memory means, it being...
US-7,359,169 Circuit for protecting integrated circuits against electrostatic discharges
A circuit is described that protects an integrated circuit from electrostatic discharges or electrical over-stress. The circuit arrangement has first and second...
US-7,358,820 Method and device for stabilizing a transfer function of a digital phase locked loop
In a method for stabilizing a transfer function of a digital phase locked loop a random digital signal is fed into the phase locked loop. The phase locked loop...
US-7,358,769 XOR circuit
An XOR circuit designed in dual rail includes four shunt transistors, wherein the shunt transistors are disposed to couple an input potential at a first input or...
US-7,358,683 Automatic PWM controlled driver circuit and method
A load driver circuit includes an output transistor configured to drive a load. The circuit further includes a power supply, and a power supply evaluation...
US-7,358,520 Semiconductor memory cell, method for fabricating it and semiconductor memory device
A semiconductor memory cell, a method for fabricating it and a semiconductor memory device. A phase change material region of a storage element of the...
US-7,358,493 Method and apparatus for automated beam optimization in a scanning electron microscope
A method and apparatus according to the present invention define optimal conditions for a scanning electron microscope (SEM), preferably a critical dimension...
US-7,358,491 Method and apparatus for the depth-resolved characterization of a layer of a carrier
The present invention relates to a method for the depth-resolved characterization of a layer of a carrier. This involves firstly producing a cutout in the layer...
US-7,358,187 Coating process for patterned substrate surfaces
The present invention provides a coating process for patterned substrate surfaces, in which a substrate (101) is provided, the substrate having a surface (105)...
US-7,358,167 Implantation process in semiconductor fabrication
A semiconductor device is formed by performing an amorphizing ion implantation to implant dopants of a first conductivity type into a semiconductor body. The...
US-7,356,781 Method for modifying design data for the production of a component and corresponding units
A method is described in which design data are prescribed which stipulate a geometrical design for a component. The design is used to produce an altered...
US-7,356,746 Embedded testing circuit for testing a dual port memory
A circuit tests a memory having a cell array accessible through first and second ports, the circuit comprising an address generation circuit for generating an...
US-7,356,741 Modular test controller with BIST circuit for testing embedded DRAM circuits
A modular test controller with a built-in self-test (BIST) circuit for testing an embedded DRAM (eDRAM) circuit is provided. The test controller includes a...
US-7,356,718 Semiconductor memory circuit and method for operating the same in a standby mode
A semiconductor memory circuit having a controller by means of which the semiconductor memory circuit can be switched into a standby mode with a reduced power...
US-7,356,324 Mobile radio receiver device
The invention is directed to a receiver arrangement, for example, in a mobile radio, which allows the use of slowly locking phase locked loops for a...
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