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Patent # Description
US-7,336,085 Current sensing circuit
A circuit arrangement for detecting a load current through a load includes a main transistor, a sensing transistor through which a load current flows that is a...
US-7,335,939 Semiconductor memory device and method of production
An array of charge-trapping memory cells and pluralities of parallel wordlines and parallel bitlines running transversely to the wordlines are arranged on a...
US-7,335,936 DRAM memory having vertically arranged selection transistors
Memory cell having a trench capacitor that is constructed in a lower region of a substantially perpendicular trench hole, and which comprises an inner and an...
US-7,335,591 Method for forming three-dimensional structures on a substrate
A method of forming a resist layer on a non-planar surface of a substrate includes placing the non-planar surface into an electrophoretic resist. While the...
US-7,335,582 Component
Semiconductor component, having a first chip arranged on a second chip, in which the first and second chips in each case have, on one of their main areas, first...
US-7,334,317 Method of forming magnetoresistive junctions in manufacturing MRAM cells
A method of forming a magnetoresistive junction in a process of manufacturing a magnetoresistive memory cell includes providing a semiconductor substrate having...
US-7,334,150 Memory module with a clock signal regeneration circuit and a register circuit for temporarily storing the...
A semiconductor memory module includes a plurality of semiconductor memory chips and bus signal lines that supply an incoming clock signal and incoming command...
US-7,333,915 Signal conditioning arrangement and method of conditioning a signal
A signal conditioning arrangement includes a sensor arrangement for sensing a measured quantity and for outputting an output signal having a first or a second...
US-7,333,577 Method for equalization of a data signal taking account of interference channels
A method for equalization of a signal is provided, wherein the equalization is of a signal that is transmitted via a data channel based on the DF method. The...
US-7,333,572 Viterbi equalization using a table memory for provision of reconstructed signal values for the calculation of...
In a method for equalization of a data signal based on the Viterbi algorithm, trellis contributions are first of all calculated for reconstructed signal values...
US-7,333,388 Multi-port memory cells
A memory array comprises memory cells of the dynamic type having a first and a second port. A cache memory is connected to the address and data paths of the...
US-7,333,383 Fuse resistance read-out circuit
Methods and apparatus for a more precise readout of fuse resistance than a conventional binary readout are provided. For some embodiments, a digital readout of...
US-7,333,382 Method and apparatus for an oscillator within a memory device
An apparatus for controlling generation of pulses for refresh operations of a memory device having a pad to transfer information and to receive signals from an...
US-7,333,358 Memory element
A memory element having a first and second logic components, each having a first input, a second input, and an output. The first input of each of the logic...
US-7,333,041 System for analog-to-digital conversion
An analog-to-digital converter system converts an analog input signal into a digital output signal. The analog input signal is converted into a first digital...
US-7,332,970 Integrated amplifier, electronic communication unit with integrated amplifier and method for operating the...
An integrated amplifier has a resonant circuit with a tuneable center frequency, in which the resonant circuit has at least one coil and at least one varactor...
US-7,332,899 Circuit arrangement for monitoring a voltage supply, and for reliable locking of signal levels when the voltage...
A circuit arrangement for monitoring an external voltage supply (VBAT1, VBAT2) and for reliable locking of a signal (Z2), which is emitted from a logic circuit...
US-7,332,812 Memory card with connecting portions for connection to an adapter
Semiconductor devices having conductive lines with extended ends and methods of extending conductive line ends by a variable distance are disclosed. An end of a...
US-7,332,788 Semiconductor power device with charge compensation structure and monolithic integrated circuit, and method for...
The invention relates to a semiconductor power device with charge compensation structure and monolithic integrated circuit, and method for fabricating it. In the...
US-7,332,725 Sensor arrangement for recording a radiation, computer tomograph comprising said sensor arrangement and...
A sensor arrangement has a layer sequence that includes a holding substrate, an auxiliary layer, a detection layer and an insulating layer. The holding substrate...
US-7,332,444 Method for smoothing areas in structures by utilizing the surface tension
A method for smoothing areas of a structure made of a first material having a predetermined first glass transition temperature on a carrier includes the steps...
US-7,332,443 Method for fabricating a semiconductor device
The present invention relates to a method for fabricating a semiconductor device. In order to provide for a high carrier mobility in an active region of the...
US-7,332,430 Method for improving the mechanical properties of BOC module arrangements
The invention relates to a method for improving the mechanical properties of BOC module arrangements in which chips have 3D structures, solder balls, .mu....
US-7,332,428 Metal interconnect structure and method
In a method of fabricating a semiconductor device, a dielectric layer is formed over a conductive region. A dual damascene structure including a trench and a via...
US-7,332,377 Manufacturing method with self-aligned arrangement of solid body electrolyte memory cells of minimum structure size
The object of providing a method for manufacturing solid body electrolyte memory cells or CB memory cells, respectively, which is suited for the simplified...
US-7,331,005 Semiconductor circuit device and a system for testing a semiconductor apparatus
Methods and apparatus for testing a semiconductor device. A testing interface is configured to interface with an external test apparatus and a device under test...
US-7,330,391 Memory having directed auto-refresh
A memory includes at least two memory banks, each memory bank including an array of memory cells including rows and columns. The memory includes a directed...
US-7,330,387 Integrated semiconductor memory device
An integrated semiconductor memory device includes a sense amplifier that is connected to a first bit line via a first output connection and is connected to a...
US-7,330,385 Integrated semiconductor memory device with adaptation of the evaluation characteristic of sense amplifiers
An integrated semiconductor memory device includes memory cells which are connected to first sense amplifiers or second sense amplifiers via in each case one bit...
US-7,330,378 Inputting and outputting operating parameters for an integrated semiconductor memory device
An integrated semiconductor memory device includes a control circuit with a mode register to store operating parameters, as well as further registers to store...
US-7,330,362 Switching converter having at least two converter stages
One embodiment of the invention relates to a switching converter having at least two converter stages, an output and an actuation circuit. The at least two...
US-7,330,077 Monolithically integrated power amplifier device
A monolithically integrated microwave frequency high power amplifier device comprises a plurality of transistors connected in a load modulation configuration...
US-7,330,063 Circuit arrangement for limiting a ringing current
A circuit arrangement for bidirectional current limiting comprises a first transistor, a second transistor, a first resistor, a first zener diode and a second...
US-7,330,053 Prestage for an off-chip driver (OCD)
A prestage for generating a control signal for an output driver of an integrated circuit, wherein the integrated circuit can be provided with a reference...
US-7,330,047 Receiver circuit arrangement having an inverter circuit
A receiver circuit arrangement includes a receiver circuit an input for receiving an input signal an output for outputting an output signal and an inverter...
US-7,330,040 Test circuitry wafer
Method and apparatus for testing a plurality of devices on a device wafer. One embodiment provides a test circuitry wafer having a first surface and a second...
US-7,329,921 Lateral semiconductor transistor
A lateral semiconductor transistor is disclosed. In one embodiment, the transistor includes a semiconductor body, in which a source region, a body region and a...
US-7,329,916 DRAM cell arrangement with vertical MOS transistors
The invention is related to a DRAM cell arrangement with vertical MOS transistors. Channel regions arranged along one of the columns of a memory cell matrix are...
US-7,329,561 Fabricating memory components (PCRAMS) including memory cells based on a layer that changes phase state
A method is describe for fabricating memory components including memory cells based on an active material of an active layer, the phase state of which can be...
US-7,328,424 Method for determining a matrix of transmission cross coefficients in an optical proximity correction of mask...
The present invention relates to a method for determining a matrix of transmission cross coefficients w for an optical modeling in an optical proximity...
US-7,328,329 Controlling processing of data stream elements using a set of specific function units
A device (1) to control processing of data elements (data_i), in which a thread is assigned to each data element (data_i), comprises a first unit (CS), which,...
US-7,328,302 Device and method for treating a state of a memory
Device for treating a memory state resulting from incomplete writing or erasing of data. The memory includes memory cells organized in a plurality of pages each...
US-7,327,766 Circuit configuration for receiving a data signal
In a clock-synchronously operated semiconductor memory, particularly a DDR SDRAM, data are read in clock-synchronously with respect to a data strobe signal in...
US-7,327,755 Method and device for storing data packets
To enable data packets, which can be present in different data transmission formats and which are to be routed in a communication network, to be stored as simply...
US-7,327,632 Interface circuit
An interface apparatus having a first and a second buffer storage unit, the first buffer storage unit being associated with a first domain and the second buffer...
US-7,327,623 Energy adjusted write pulses in phase-change memories
A memory cell device that includes a plurality of phase-change memory cells, at least one write pulse generator, and at least one temperature sensor. The...
US-7,327,603 Memory device including electrical circuit configured to provide reversible bias across the PMC memory cell to...
Methods and apparatuses for programming a programmable metallization cell (PMC) memory cell are provided. A memory device includes a programmable metallization...
US-7,327,593 ROM memory cell having defined bit line voltages
The invention relates to a ROM memory cell of a ROM memory, which provides a first predetermined potential or a second predetermined potential in the driven...
US-7,327,193 Method for setting an amplifier, and corresponding amplifier circuit
An amplifier and method of setting the amplifier is presented. The amplifier is set by setting a mean value between voltage values at first and second outputs of...
US-7,327,152 Integrated test circuit arrangement and test method
An integrated test circuit arrangement is provided that contains integrated test structures, at least one integrated heating element, an integrated detection...
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