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Semiconductor device with a rewiring level and method for producing the
A semiconductor device includes a plastic package, at least one semiconductor chip and a rewiring level. The rewiring level includes an insulating layer and a...
The object of providing a non-volatile semiconductor memory that stands out by good scalability and a high retention time as well as ensures low switching...
Process for vertically patterning substrates in semiconductor process
technology by means of inconformal deposition
On a substrate surface, which has been patterned in the form of a relief, of a substrate, typically of a semiconductor wafer, a deposition process is used to...
Semiconductor wafer with a wiring structure, a semiconductor component,
and methods for their production
A semiconductor wafer is provided with a wiring structure, and semiconductor chip positions arranged in rows and columns. The semiconductor wafer has at least...
CMOS transistor and method of manufacture thereof
A CMOS device with transistors having different gate dielectric materials and a method of manufacture thereof. An aluminum-based material is used as a gate...
NROM semiconductor memory device and fabrication method
An NROM semiconductor memory device and fabrication method are disclosed. According to one aspect, a method for fabricating an NROM semiconductor memory device...
Ferromagnetic liner for conductive lines of magnetic memory cells and
methods of manufacturing thereof
Methods of forming ferromagnetic liners on the top surface and sidewalls of conductive lines of magnetic memory devices. The ferromagnetic liners increase the...
Gassing-free exposure mask
The present invention relates to an exposure mask for structuring a photoresist layer on a substrate wafer, in which an inorganic adhesive is used as an adhesive...
Apparatus and method for detecting a tire deformation of a vehicle tire
An apparatus for detecting a tire deformation of a vehicle tire includes a tire pressure sensor for sensing a tire pressure, a signal processor configured to...
Testing memory units in a digital circuit
A method of testing a memory unit in a digital circuit includes storing a test pattern on a register of the digital circuit. The register is then selected by...
Circuit arrangement and method for compensating for disturbances in a
signal generated by means of discrete...
A circuit arrangement for compensating for disturbances in a signal generated by means of discrete multitone modulation includes a multiplicity of adder circuits...
Memory device and method for operating a memory device
A memory device (1) includes a memory array (2). The memory array (2) has at least one memory area (5) that includes a plurality of conductive lines (3) and a...
Methods for generating a reference voltage and for reading a memory cell
and circuit configurations...
A method and a circuit configuration for generating a reference voltage in a resistive semiconductor memory includes generating a reference voltage by connecting...
DQS signaling in DDR-III memory systems without preamble
A data transmission system, particularly as part of a DDR-III memory chip communication circuit, performs a data transmission operation without preamble. The...
Circuit arrangement for protection against electrostatic discharge and
voltage regulating device having a...
A circuit arrangement for protection against electrostatic discharge for a field-effect transistor is disclosed. The arrangement includes a first and a second...
Successive approximation analog/digital converter
A successive approximation analog/digital converter converting an analog input signal into a digital output value by means of a plurality of successive...
Power output stage
A class D power output stage for switching a supply voltage comprises a limiting transistor with a controllable path and a control terminal, a complementary...
Current regulator having a transistor and a measuring resistor
The invention relates to a current regulator having the following features: a first semiconductor body (1; 1') having a first and second terminal contact (11,...
Circuit and method for calculating a logical combination of two input
A circuit for calculating a logical combination of two input operands includes a first input for receiving a first dual rail signal having data values of the...
CMOS circuit arrangement
In an embodiment of the invention, a CMOS circuit arrangement is provided. The CMOS circuit arrangement includes a PMOS logic circuit providing a logic function,...
Device for measurement and analysis of electrical signals of an integrated
According to the invention, one or more external test connection contact points (pads; pins; balls), are provided in an integrated circuit component (chip) (1),...
Drive circuit for two switching converter stages in a voltage converter
A drive circuit is disclosed including a first feedback circuit designed to generate a first feedback signal from a first voltage to be controlled and a first...
Electronic component with semiconductor chips, electronic assembly
composed of stacked semiconductor chips, and...
An electronic component includes a semiconductor chip with an active front face and a passive rear face, with contact connections and contact surfaces...
Device having a useful structure and an auxiliary structure
The present invention provides a device having a useful structure which is arranged on a substrate and has a useful structure side edge. In addition, an...
Capacitor assembly having a contact electrode encircling or enclosing in
rectangular shape an effective...
A capacitor assembly has a substrate, a first conductive auxiliary layer on the substrate, a capacitor dielectric, a second conductive auxiliary layer and a...
Standby current reduction over a process window with a trimmable well bias
An integrated circuit device including a plurality of MOSFETs of similar type and geometry is formed on a substrate with an ohmic contact, and an adjustable...
Method for controlling a thickness of a first layer and method for
adjusting the thickness of different first...
A method for controlling a thickness of a first layer of an electrical contact of a semiconductor device, whereby the semiconductor device comprises a...
Capacitorless 1-transistor DRAM cell and fabrication method
A semiconductor device is fabricated by forming a trench in a semiconductor body. A region of dielectric material is formed within at least a lower portion of...
Semiconductor memory device with a capacitor formed therein and a method
for forming the same
To integrate a capacitor device (40) into the region of a semiconductor memory device with a particularly small number of process steps, a lower electrode device...
Method for producing an electronic device connected to a printed circuit
A configuration and also a method for the configuration in which, the configuration has at least one electronic device with associated contact connections and at...
Method of testing multiple modules on an integrated circuit
An integrated circuit (20) comprises a plurality of processing modules (3, 5, 7) which interact during the normal operation of the integrated circuit. Switches...
Method for automatically detecting the clock frequency of a system clock
pulse for the configuration of a...
The present invention provides a method for automatic identification of the clock frequency of a system clock (15) for the configuration of a peripheral device...
Device connected to a bus for storing information utilized to allocate
priority to data stored in storage...
A device that is connected to a bus can transmit data to one or more other devices and/or can receive data from other devices, through the bus, includes storage...
Monitoring device for monitoring internal signals during initialization of
an electronic circuit
The invention provides a device for monitoring electronic circuit units during an initialization phase. The device has at least one internal data line (103) for...
Maximum likelihood estimation of the channel coefficients and of the DC
offset in a digital baseband signal of...
The proposed iterative method concurrently calculates maximum likelihood estimated values for the channel coefficients (h.sub.0, . . . , h.sub.L; .theta..sub.h)...
Devices for reducing the dynamic range of signals in transmitters of
A device reduces the dynamic range of a signal at a first point along a signal processing direction in a transmitter of a communication system. The device...
Device for correcting a receiving signal
The invention relates to a device for correcting a receiver signal which is associated with an emission signal transmitted in a distorted transmission system....
Test mode method and apparatus for internal memory timing signals
A method of testing internal signals of a memory for timing marginalities which may result in unstable operation includes: delaying internal address signals of...
Memory system and method of accessing memory chips of a memory system
A memory system and method is discussed. The memory system includes a memory controller and at least one memory module on which a certain number of semiconductor...
Configurable embedded processor
A configurable processor architecture uses a common simulation database for multiple processor configurations to reduce the cost of producing customized...
Phase change memory array having equalized resistance
A memory includes memory cells, a first line coupled to the memory cells, and a second line coupled to the memory cells. A series resistance due of the first...
Method for driving a semiconductor switch and circuit configuration with a
A method for driving a semiconductor switch with load current limiting and thermal protection whose maximum load current is limited and which switches off when a...
Apparatus for projecting a pattern into an image plane
An improvement of the imaging quality with simultaneous transfer of line-space gratings and peripheral structures including a MUX space is achieved using a...
BAW duplexer without phase shifter
A duplexer for connection with an antenna comprises an antenna port, a transmitting filter comprising bulk acoustic wave (BAW) resonators having a first antenna...
Filter circuit array
A filter circuit array is disclosed. In one embodiment, the filter circuit array includes a higher-order filter circuit array, wherein one energy storage per...
SC circuit arrangement
The invention relates to a linear SC circuit arrangement using integrated deep submicron technology, having at least one switched capacitor circuit which is...
DLL circuit for providing an adjustable phase relationship with respect to
a periodic input signal
The invention relates to a DLL circuit for providing an adjustable time delay of a periodic input signal, said circuit having controllable delay elements which...
Gate drive circuit for an insulated gate power transistor
The invention relates to a gate drive circuit for, and in combination with, an insulated gate power transistor. The drive circuit is connected to the gate...
Switching converter and method for driving a switch in a switching
A switching converter has a switch, a rectifier arrangement connected to the switch, a controller arrangement providing a control signal dependent on the output...
Connection, configuration, and production of a buried semiconductor layer
A power transistor has a semiconductor volume including a plurality of transistor cells connected in parallel, a laterally oriented, highly conductive...