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Patent # Description
US-7,384,822 Package for semiconductor components and method for producing the same
The invention relates to a packaging for semiconductor components such as FBGA packages in BOC technology or the like, wherein at least the back and the lateral...
US-7,384,698 Metal article intended for at least partially coating with a substance and a method for producing the same
A metal article intended for at least partially coating with a substance, which includes a metal solder, a plastic, a glass, or a ceramic. The metal article...
US-7,384,002 Chip card and chip card security device
The invention relates to a chip card security device, a procedure to be used in securing a chip card, as well as a chip card (1), comprising: at least one memory...
US-7,383,416 Method for setting a second rank address from a first rank address in a memory module
A method for setting an address of a rank in a memory module having a number of memory chips distributed along a byte lane includes setting the first memory chip...
US-7,383,144 Method and apparatus for calibration of an on-chip temperature sensor within a memory device
According to embodiments of the present invention, an automatic trim or calibration for a temperature sensor of a chip or memory device is performed on that...
US-7,382,673 Memory having parity generation circuit
A memory includes a column segment including memory cells along word lines, and a parity generation circuit configured to receive a first serial data stream of...
US-7,382,669 Semiconductor memory component and method for testing semiconductor memory components
A semiconductor component and method of testing a semiconductor component is disclosed. The invention relates to the parallel testing of semiconductor memory...
US-7,382,025 ESD protection structure with lower maximum voltage
A semiconductor structure for protecting integrated circuits from ESD pulses includes a semiconductor substrate of a first conductivity type and with a first...
US-7,381,645 Method for the production of an integrated circuit bar arrangement comprising a metal nitride layer and...
The document explains, inter alia, a method in which a titanium nitride layer is removed by wet chemical means (106). Following removal of the titanium nitride,...
US-7,381,576 Method and apparatus for monitoring precision of water placement alignment
A method for monitoring precision of placement of semiconductor wafers in a semiconductor processing apparatus includes measuring thickness of an insulating film...
US-7,381,574 Method of forming dual interconnects in manufacturing MRAM cells
A method of forming dual interconnects in a magnetoresistive memory cell includes: providing an intermediate product including: a metallization layer including...
US-RE40,352 Switch mode power supply with reduced switching losses
The invention relates to a switching transistor presenting reduced switching losses. In the switching transistor, output capacitance is very high when...
US-7,380,182 Method and apparatus for checking output signals of an integrated circuit
Apparatus and method for checking output signals of an integrated circuit are provided. One embodiment provides a method for checking whether signals are output...
US-7,379,766 CMOS-process compatible high-DC surface coating for capacitive detection and stimulation of biological tissues
Biochip for capacitive stimulation and/or detection of biological tissues. The biochip has a carrier structure, at least one stimulation and/or sensor device,...
US-7,379,727 RF front-end receiver
An RF front-end receiver comprises a low noise amplifier and a local oscillator driver, which are connected to respective input ports of a mixer which comprises...
US-7,379,713 Method for wireless data interchange between circuit units within a package, and circuit arrangement for...
Method for wireless data interchange between circuit units within a package, and circuit arrangement for performing the method. The invention provides a circuit...
US-7,379,383 Methods of DDR receiver read re-synchronization
A method for reading data is provided. The method includes generating two or more pulses from a first clock signal by which the data to be read is received,...
US-7,379,373 Voltage supply circuit, in particular for a DRAM memory circuit, as well as a method for controlling a supply...
A voltage supply circuit for providing an internal supply voltage in an integrated circuit is provided. The voltage supply circuit comprises a supply source for...
US-7,379,339 Device and procedure for measuring memory cell currents
The invention relates to a procedure and a device for measuring memory cell currents, in particular for non-volatile memory components, where the device has a...
US-7,379,005 Apparatus and method for spectrally shaping a reference clock signal
Clock signal jitter detection circuit for detecting a clock signal jitter in a reference clock signal (CLK), having a switched-capacitor reference ...
US-7,378,998 Correction of static mismatch errors in a D/A converter
Methods, articles of manufacture and systems for the correction of static mismatch errors in D/A converters, where an input word, being the digital ...
US-7,378,905 Differential driver circuit
A current-saving differential wideband driver circuit comprises a differential input amplifier for amplifying a differential input signal to produce a...
US-7,378,892 Device for setting a clock delay
A device for setting a clock delay is proposed, wherein delayed output clock signals are generated with the aid of delaying means by delaying an input clock...
US-7,378,807 Drive circuit for a fluorescent lamp with a diagnosis circuit, and method for diagnosis of a fluorescent lamp
A drive circuit for at least one fluorescent lamp has a half-bridge circuit for production of a supply voltage a resonant tuned circuit coupled to the...
US-7,378,741 Semiconductor component and corresponding fabrication/mounting method
A semiconductor component (1) has a substrate (21) and a structure (22, 23) formed from semiconductor/insulator/conductor layers (24 to 26) on/in the substrate...
US-7,378,700 Self-aligned V0-contact for cell size reduction
An FeRAM comprising includes a ferroelectric material sandwiched between a top electrode and a bottom electrode. A V0-contact provides an electrical connection...
US-7,378,321 Method for patterning a semiconductor component
In a method for patterning a semiconductor component a first cover layer is applied to a first region and a second region of a semiconductor component being...
US-7,376,925 Method for production of a standard cell arrangement, and apparatus for carrying out the method
A standard cell arrangement can be produced by automatically determining a distance between at least two standard cells in at least one standard cell row. The...
US-7,376,802 Memory arrangement
The present invention relates to a memory arrangement having a controller and having at least one memory device. Data signals, control signals and address...
US-7,376,689 Method and apparatus for reducing the crest factor of a signal
A method and apparatus for reducing the crest factor of a signal uses a plurality of partial correction signals having respective predetermined frequencies. For...
US-7,376,512 Method for determining an optimal absorber stack geometry of a lithographic reflection mask
The present invention relates to a method for determining an optimal absorber stack geometry of a lithographic reflection mask comprising a reflection layer and...
US-7,376,117 Interleaving circuit for a multiband OFDM transceiver
Interleaving circuit for a multiband OFDM (orthogonal frequency division multiplexing) transceiver of a ultra wide band wireless personal access network...
US-7,376,026 Integrated semiconductor memory having sense amplifiers selectively activated at different timing
An integrated semiconductor memory includes a memory cell array in which first sense amplifiers are arranged on a right-hand side of the memory cell array and...
US-7,376,018 Non-volatile memory device with single transistor memory cell
A non-volatile memory device includes a plurality of word lines, a plurality of sense lines, and a plurality of non-volatile memory cells. Each memory cell...
US-7,375,999 Low equalized sense-amp for twin cell DRAMs
Embodiments of the invention provide a method and apparatus for accessing a twin cell memory device. In one embodiment, a twin memory cell is accessed using a...
US-7,375,983 Circuit board for reducing crosstalk of signals
A circuit board includes a first group of layers located close to a top side of the circuit board, and a second group of layers located close to an underside of...
US-7,375,971 Memory module with an electronic printed circuit board and a plurality of semiconductor chips of the same type
In a first embodiment, the invention provides a memory module having an electronic printed circuit board and a plurality of semiconductor chips of the same type...
US-7,375,576 Log circuit and highly linear differential-amplifier circuit
A log circuit receives an operated current signal and a reference current signal at respective inputs and comprises an operand log circuit including a first...
US-7,375,508 Device and a process for the calibration of a semiconductor component test system
A device and a process for the calibration of a semi-conductor component test systemThe invention relates to a process and a device for the calibration of a...
US-7,375,434 Semiconductor chip with flexible contacts at a face
The present invention relates to a semiconductor chip comprising a semiconductor element, at least a conducting line and a contact area being arranged on the...
US-7,375,395 Vertical field-effect transistor in source-down structure
The invention relates to a vertical field-effect transistor in source-down structure, in which the active zones (10, 7, 11) are introduced from trenches (5, 8,...
US-7,375,387 Method for producing semiconductor memory devices and integrated memory device
The invention provides an integration scheme for a memory cell array, especially a charge-trapping memory cell array, comprising an architecture of local...
US-7,375,029 Method for fabricating contact holes in a semiconductor body and a semiconductor structure
A method for fabricating contact holes in a semiconductor body proceeds from a structure in which: a plurality of trenches isolated from one another by mesa...
US-7,374,952 Methods of patterning a magnetic stack of a magnetic memory cell and structures thereof
Methods of patterning a magnetic stack of a magnetic memory cell and structures thereof. At least the top magnetic material layer of a magnetic stack is...
US-7,373,583 ECC flag for testing on-chip error correction circuit
The present invention includes an error correction circuit with a data memory, a control circuit, a parity memory, and a recorder. The data memory is configured...
US-7,373,562 Memory circuit comprising redundant memory areas
The invention relates to a memory circuit comprising regular memory areas and redundant memory areas, redundancy circuits in each case being assigned to the...
US-7,373,445 Method and apparatus for allocating bus access rights in multimaster bus systems
A method for allocating bus access rights is used in a multimaster bus system wherein addresses are explicitly allocated to master devices and each master device...
US-7,372,923 Method for equalization of a payload signal, taking into account an interference source
In a method for equalization of a signal which is transmitted via a payload channel taking into account at least one interference channel, the trellis diagram...
US-7,372,918 Transmission device with adaptive digital predistortion, transceiver with transmission device, and method for...
The invention provides a transmission device having adaptive digital predistortion, which has a transmission path and a feedback path. The transmission path...
US-7,372,750 Integrated memory circuit and method for repairing a single bit error
The invention relates to an integrated memory circuit having a memory cell array comprising memory cells arranged on word lines and bit lines, and having a...
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