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Patent # Description
US-7,391,245 Delay locked loop and method for setting a delay chain
A delay locked loop includes a delay chain that contains a plurality of series-connected delay cells, a phase detector arrangement that contains a plurality of...
US-7,391,121 Semiconductor device with a number of bonding leads and method for producing the same
A semiconductor device (7) has a number of bonding leads (1, 2, 3) with more than one individual bonding lead (1) being arranged on an individual contact area...
US-7,391,107 Signal routing on redistribution layer
A semiconductor wafer has a dielectric layer, a metal last layer, a passivation layer, and a redistribution layer. The metal last layer is formed over the...
US-7,391,103 Electronic module having plug contacts and method for producing it
The invention relates to an electronic module having plug contacts, which has a semiconductor chip embedded in a plastics composition with its rear side and its...
US-7,391,084 LDMOS transistor device, integrated circuit, and fabrication method thereof
An LDMOS transistor device in an integrated circuit comprises a semiconductor substrate (10), a gate region (1) including a gate semiconductor layer region (2;...
US-7,391,080 LDMOS transistor device employing spacer structure gates
An integrated LDMOS transistor comprises a semiconductor substrate (11), an LDMOS gate region (17), LDMOS source (14) and drain (15) regions, and a channel...
US-7,391,050 Phase change memory device with thermal insulating layers
A memory device is described an active material configured to be placed in a more or less conductive state by means of appropriate switching processes. The...
US-7,390,742 Method for producing a rewiring printed circuit board
The invention relates to a method for producing a rewiring printed circuit board with a substrate wafer having passage connections between a first and a second...
US-7,390,737 Method for filling a contact hole and integrated circuit arrangement with contact hole
A method in which a base layer is deposited in a contact hole region under a protective gas, where base layer contains a nitride as main constituent. After the...
US-7,390,713 Method for forming trench memory cell structures for DRAMS
One embodiment of the invention relates to a method for forming trench memory cell structures having trench capacitors and planar selection transistors. An...
US-7,390,703 Method for through-plating field effect transistors with a self-assembled monolayer of an organic compound as...
A method for through-plating field effect transistors with a self-assembled monolayer of an organic compound as gate dielectric includes through-plating by...
US-7,389,903 Device and method for soldering contacts on semiconductor chips
A device for soldering contacts on semiconductor chips. A chip is held on a chip mount by a chuck and is heated from a side facing away from the wafer by means...
US-7,389,696 Measuring device with a microsensor and method for producing the same
A measuring apparatus includes at least one microsensor having at least two chambers filled with a gas. The chambers are connected to one another by at least one...
US-7,389,458 Method and apparatus for the memory self-test of embedded memories in semiconductor chips
Method for the memory self-test of embedded memories (2, 3, 4) in semiconductor chips (1), a memory address range (8) being assigned to a memory (2) to be tested...
US-7,388,885 Splitter circuit
A splitter circuit (19) serves to combine on the transmission side signals which are to be transmitted in different frequency bands (A-C), as well as to separate...
US-7,388,734 Integrated circiut arrangement
Integrated circuit arrangement having first and second signal input pads, to which a differential input signal is applied, and first and second signal outputs,...
US-7,388,667 Optical determination of resistivity of phase change materials
A system includes a non-contacting optical measurement instrument and a controller. The non-contacting optical measurement instrument is configured to obtain a...
US-7,387,930 Method of fabricating a bottle trench and a bottle trench capacitor
A method of fabricating a bottle trench and a bottle trench capacitor. The method including: providing a substrate; forming a trench in the substrate, the trench...
US-7,386,812 Logic basic cell and logic basic cell arrangement
Logic basic cell and logic basic cell arrangement having a plurality of logic basic cells. A logic basic cell includes at least six data signal inputs, a first...
US-7,386,776 System for testing digital components
In order to test digital modules with functional elements, these are divided into test units (3) which respectively have inputs and outputs. Alternating test...
US-7,386,769 On chip diagnosis block with mixed redundancy
On chip diagnosis method and on chip diagnosis block with mixed redundancy (IO redundancy and word-register redundancy) is provided. During a BIST (Built-In Self...
US-7,386,696 Semiconductor memory module
The invention relates to a semiconductor memory module having a plurality of memory chips arranged in at least one row and at least one buffer chip which drives...
US-7,386,059 Device for processing signals in a mobile station
A device for processing signals may be designed as a transmitting and receiving arrangement or exclusively as a receiving arrangement, and has a baseband...
US-7,385,837 Nonvolatile memory cell and methods for operating a nonvolatile memory cell
A nonvolatile memory cell (1) can be integrated in space-saving fashion into a semiconductor circuit (10) intended for volatile storage with the aid of volatile...
US-7,385,676 Mask set having separate masks to form different regions of integrated circuit chips, exposure system including...
A mask set for the production of integrated circuit chips, wherein a first mask has first features that form inner cell regions and a second mask has second...
US-7,385,485 Smart time tire monitoring system
A tire monitoring system and associated method includes a plurality of tire sensor modules configured to transmit tire data in a wireless fashion at a...
US-7,385,404 Arrangement and method for testing a capacitance array in an integrated circuit
An arrangement for testing a plurality of capacitances in a capacitance array of an integrated circuit includes a power supply and a means for cyclically...
US-7,385,394 Integrated magnetic sensor component
A sensor component used to measure a magnetic field strength is disclosed. In one embodiment, the sensor component contains a plurality of leads and a sensor...
US-7,385,243 Floating gate memory cell with a metallic source/drain and gate, and method for manufacturing such a floating...
Floating gate memory cell having a first layer with first and second source/drain regions and a channel region arranged between and next to the first and second...
US-7,384,822 Package for semiconductor components and method for producing the same
The invention relates to a packaging for semiconductor components such as FBGA packages in BOC technology or the like, wherein at least the back and the lateral...
US-7,384,698 Metal article intended for at least partially coating with a substance and a method for producing the same
A metal article intended for at least partially coating with a substance, which includes a metal solder, a plastic, a glass, or a ceramic. The metal article...
US-7,384,002 Chip card and chip card security device
The invention relates to a chip card security device, a procedure to be used in securing a chip card, as well as a chip card (1), comprising: at least one memory...
US-7,383,416 Method for setting a second rank address from a first rank address in a memory module
A method for setting an address of a rank in a memory module having a number of memory chips distributed along a byte lane includes setting the first memory chip...
US-7,383,144 Method and apparatus for calibration of an on-chip temperature sensor within a memory device
According to embodiments of the present invention, an automatic trim or calibration for a temperature sensor of a chip or memory device is performed on that...
US-7,382,673 Memory having parity generation circuit
A memory includes a column segment including memory cells along word lines, and a parity generation circuit configured to receive a first serial data stream of...
US-7,382,669 Semiconductor memory component and method for testing semiconductor memory components
A semiconductor component and method of testing a semiconductor component is disclosed. The invention relates to the parallel testing of semiconductor memory...
US-7,382,025 ESD protection structure with lower maximum voltage
A semiconductor structure for protecting integrated circuits from ESD pulses includes a semiconductor substrate of a first conductivity type and with a first...
US-7,381,645 Method for the production of an integrated circuit bar arrangement comprising a metal nitride layer and...
The document explains, inter alia, a method in which a titanium nitride layer is removed by wet chemical means (106). Following removal of the titanium nitride,...
US-7,381,576 Method and apparatus for monitoring precision of water placement alignment
A method for monitoring precision of placement of semiconductor wafers in a semiconductor processing apparatus includes measuring thickness of an insulating film...
US-7,381,574 Method of forming dual interconnects in manufacturing MRAM cells
A method of forming dual interconnects in a magnetoresistive memory cell includes: providing an intermediate product including: a metallization layer including...
US-RE40,352 Switch mode power supply with reduced switching losses
The invention relates to a switching transistor presenting reduced switching losses. In the switching transistor, output capacitance is very high when...
US-7,380,182 Method and apparatus for checking output signals of an integrated circuit
Apparatus and method for checking output signals of an integrated circuit are provided. One embodiment provides a method for checking whether signals are output...
US-7,379,766 CMOS-process compatible high-DC surface coating for capacitive detection and stimulation of biological tissues
Biochip for capacitive stimulation and/or detection of biological tissues. The biochip has a carrier structure, at least one stimulation and/or sensor device,...
US-7,379,727 RF front-end receiver
An RF front-end receiver comprises a low noise amplifier and a local oscillator driver, which are connected to respective input ports of a mixer which comprises...
US-7,379,713 Method for wireless data interchange between circuit units within a package, and circuit arrangement for...
Method for wireless data interchange between circuit units within a package, and circuit arrangement for performing the method. The invention provides a circuit...
US-7,379,383 Methods of DDR receiver read re-synchronization
A method for reading data is provided. The method includes generating two or more pulses from a first clock signal by which the data to be read is received,...
US-7,379,373 Voltage supply circuit, in particular for a DRAM memory circuit, as well as a method for controlling a supply...
A voltage supply circuit for providing an internal supply voltage in an integrated circuit is provided. The voltage supply circuit comprises a supply source for...
US-7,379,339 Device and procedure for measuring memory cell currents
The invention relates to a procedure and a device for measuring memory cell currents, in particular for non-volatile memory components, where the device has a...
US-7,379,005 Apparatus and method for spectrally shaping a reference clock signal
Clock signal jitter detection circuit for detecting a clock signal jitter in a reference clock signal (CLK), having a switched-capacitor reference ...
US-7,378,998 Correction of static mismatch errors in a D/A converter
Methods, articles of manufacture and systems for the correction of static mismatch errors in D/A converters, where an input word, being the digital ...
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