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Patent # Description
US-7,372,334 Output match transistor
A power transistor, having: a semiconductor having an electrode formed thereon, wherein the electrode comprises a plurality of interdigitated transistors each...
US-7,372,331 Receiver circuit
A receiver circuit for receiving and forwarding data signals comprises at least one first and one second input to be used to inject an external digital data...
US-7,372,103 MOS field plate trench transistor device
A MOS field plate trench transistor device is disclosed. In one embodiment, in order to obtain a lowest possible on resistance, in the case of a MOS field plate...
US-7,372,095 Integrated semiconductor circuit comprising a transistor and a strip conductor
An integrated semiconductor circuit includes a transistor and a strip conductor (11). The transistor includes a first (1) and a second source/drain region (2)...
US-7,372,093 DRAM memory with vertically arranged selection transistors
The invention relates to a semiconductor memory, particularly a DRAM, in which the memory cells in each case have a trench capacitor arranged in a lower area of...
US-7,372,072 Semiconductor wafer with test structure
The invention relates to a semiconductor wafer (1) having a plurality of first sawing regions (201-211) running parallel to one another in a first direction (X)...
US-7,371,657 Method for forming an isolating trench with a dielectric material
The present invention relates to a method of forming an isolating trench of a semiconductor device with a dielectric material, and to a method of forming an...
US-7,371,650 Method for producing a transistor structure
A method for fabricating a transistor structure with a first and a second bipolar transistor having different collector widths is presented. The method includes...
US-7,371,645 Method of manufacturing a field effect transistor device with recessed channel and corner gate device
Fabrication of recessed channel array transistors (RCAT) with a corner gate device includes forming pockets between a semiconductor fin that includes a gate...
US-7,371,012 Optoelectronic module and plug arrangement
A compact optoelectronic module that prevents undesirable heating by locating the electrical drive and/or receiving (control) circuit outside of the housing...
US-7,370,313 Method for optimizing a photolithographic mask
The invention relates to a method for optimizing a mask layout pattern comprising at least one structural feature. First a desired layout pattern is provided....
US-7,370,303 Method for determining the arrangement of contact areas on the active top side of a semiconductor chip
In the case of a method according to the invention for determining the arrangement of contact areas on the active top side of a semiconductor chip arranged in or...
US-7,369,969 Holding device for a sensor signal, method for forwarding a sensor signal and computer program
A holding device for a sensor signal comprises a signal input receiving a sensor signal, a signal output and a storage device coupled to the signal input and...
US-7,369,602 Adaptive channel estimation by means of variation of the integration length during the despreading of...
In the method, the received spread-coded signal sequence r.sub.k(i) is first of all correlated with the spread-coded training symbol sequence in a correlator...
US-7,369,568 ATM-port with integrated ethernet switch interface
An ATM-port module for an ATM-node having an Ethernet switch includes an ATM-controller; and an Ethernet-switch interface connecting it to the Ethernet switch....
US-7,369,426 Magnetoresistive memory cell with dynamic reference layer
The present invention relates to an arrangement for increasing a relative change in resistance of a magnetoresistive memory cell (17) having in each case a...
US-7,369,382 Integrated circuit with an undervoltage detector
An integrated circuit arrangement includes connection terminals, an undervoltage detector, and at least one circuit unit. The connection terminals are configured...
US-7,368,948 Integrated receiver circuit
An integrated receiver circuit for amplifying an input signal based on a reference signal includes two voltage converters to respectively convert the input and...
US-7,368,833 Multichannel DC/DC converter
An apparatus which has a first stage with an input circuit with an inductive element (1), a second stage with a number of output circuits with loads (3, 4, 5)...
US-7,368,824 Diffusion solder position, and process for producing it
A diffusion solder position between two parts has intermetallic phases formed by two solder components. Nanoparticles of a filler material are ...
US-7,368,804 Method and apparatus of stress relief in semiconductor structures
A method, apparatus and system are provided for relieving stress in the via structures of semiconductor structures whenever a linewidth below a via is larger...
US-7,368,752 DRAM memory cell
A DRAM memory cell is provided with a selection transistor, which is arranged horizontally at a semiconductor substrate surface and has a first source/drain...
US-7,368,390 Photolithographic patterning process using a carbon hard mask layer of diamond-like hardness produced by a...
A carbon hard mask layer is applied to a substrate to be patterned by means of a plasma-enhanced deposition process in such a manner that it has a hardness...
US-7,368,385 Method for producing a structure on the surface of a substrate
The present invention relates to a method for producing a structure serving as an etching mask on the surface of a substrate. In this case, a first method...
US-7,368,375 Electronic component with compliant elevations having electrical contact areas and method for producing it
An electronic component includes compliant elevations having electrical contact areas for contact-connecting the component to an electronic circuit. The...
US-7,368,356 Transistor with doped gate dielectric
A transistor and method of manufacture thereof. A semiconductor workpiece is doped before depositing a gate dielectric material. Using a separate anneal process...
US-7,368,350 Memory cell arrays and methods for producing memory cell arrays
A method for fabricating stacked non-volatile memory cells and non-volatile memory cell arrays are disclosed. A semiconductor wafer is provided having a...
US-7,368,341 Semiconductor circuit arrangement with trench isolation and fabrication method
An explanation is given of, inter alia, a circuit arrangement containing a trench which penetrates through a charge-storing layer (18) and a doped semiconductor...
US-7,368,322 Method for mounting a chip on a base and arrangement produced by this method
An electronic component includes a base and a chip attached to the base by a plurality of adhesive pads that are spaced apart from one another and are arranged...
US-7,368,314 Method for fabricating a resistive memory
A method for fabricating a resistively switching memory cell is provided. The method includes the following steps: depositing a first electrode, applying a layer...
US-7,368,299 MTJ patterning using free layer wet etching and lift off techniques
Methods of patterning magnetic tunnel junctions (MTJ's) of magnetic memory devices, wherein the second magnetic layer or free layer of a magnetic stack may be...
US-RE40,292 Bandpass filter
The bandpass filter has a comparatively large pass bandwidth, with, at the same time, comparatively steep edges up to the stop band and low attenuation in the...
US-7,366,819 Fast unaligned cache access system and method
A cache unit multiple memory towers, which can be independently addressed. Cache lines are divided among multiple towers. Furthermore, physical lines of the...
US-7,366,047 Method and apparatus for reducing standby current in a dynamic random access memory during self refresh
A dynamic random access memory including a first dynamic random access memory cell, a second dynamic random access memory cell to be refreshed, a sense...
US-7,366,031 Memory arrangement and method for addressing a memory
A memory arrangement includes a plurality of switching elements arranged in the form of a binary tree. The memory elements are supplied with data to be stored by...
US-7,366,002 Method and storage device for the permanent storage of data
It is proposed that bitline inversion coding data be integrally stored in the structure of a column multiplexer of a storage device. For this purpose,...
US-7,365,990 Circuit board arrangement including heat dissipater
A circuit board arrangement includes a heat dissipater. A cooling body is arranged near a first circuit board and a second circuit board. Both circuit boards...
US-7,365,662 DC-offset correction circuit for a communication system and method of correcting a DC-offset in a communication...
A DC-offset correction circuit includes an analog circuit to generate a plurality of analog offset-correction signal values, each of which are assigned to a hop...
US-7,365,619 BAW apparatus
A description is given of a BAW apparatus having a first BAW resonator and a second BAW resonator which are connected antiparallel to one another so as to reduce...
US-7,365,606 Receiving amplifier, in particular for television receivers, and use of the receiving amplifier
A receiving amplifier includes a semiconductor body with a first node, a second node and an amplifier circuit. The amplifier includes at least one field-effect...
US-7,365,601 Amplifier for amplifying a signal
An amplifier for amplifying a signal which is applied to a signal input having a first pair of transistors (10), which is connected to the signal input and which...
US-7,365,554 Integrated circuit for determining a voltage
An integrated circuit includes a current generator circuit with a first input terminal for applying a reference voltage and a second input terminal for applying...
US-7,365,547 Circuit arrangement for a corrosion protection current feed and for a line test for two-wire lines
A circuit arrangement for a line test and for feeding a corrosion protection current into a two-wire line comprises a controllable ramp generator for producing a...
US-7,365,438 Semiconductor device with semiconductor components connected to one another
The present invention relates to a semiconductor device which provides a shortest possible connection between two semiconductor components 10a and 10b arranged...
US-7,365,402 LDMOS transistor
An LDMOS semiconductor transistor structure comprises a substrate having an epitaxial layer of a first conductivity type, a source region extending from a...
US-7,365,382 Semiconductor memory having charge trapping memory cells and fabrication method thereof
A semiconductor memory having charge trapping memory cells, where the direction of current flow of each channel region of the memory transistors runs...
US-7,365,025 Methods of forming dual-damascene interconnect structures on semiconductor substrates using multiple...
Methods of forming integrated circuit devices include patterning an electrically insulating layer to support dual-damascene interconnect structures therein. The...
US-7,364,999 Method for interconnecting semiconductor components with substrates and contact means
A semiconductor component includes a substrate having a plurality of compliant contact bumps formed over a surface thereof. A semiconductor chip has a plurality...
US-7,364,975 Semiconductor device fabrication methods
Methods of fabricating semiconductor devices are disclosed. In a preferred embodiment, a method of fabricating a semiconductor device includes providing a...
US-RE40,275 Method for producing a memory cell
A method for producing a memory cell includes masking a desired polysilicon structure with an oxidation-inhibiting layer, preferably a nitride layer. The...
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