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Semiconductor memory component and method for testing semiconductor memory
A semiconductor component and method of testing a semiconductor component is disclosed. The invention relates to the parallel testing of semiconductor memory...
ESD protection structure with lower maximum voltage
A semiconductor structure for protecting integrated circuits from ESD pulses includes a semiconductor substrate of a first conductivity type and with a first...
Method for the production of an integrated circuit bar arrangement
comprising a metal nitride layer and...
The document explains, inter alia, a method in which a titanium nitride layer is removed by wet chemical means (106). Following removal of the titanium nitride,...
Method and apparatus for monitoring precision of water placement alignment
A method for monitoring precision of placement of semiconductor wafers in a semiconductor processing apparatus includes measuring thickness of an insulating film...
Method of forming dual interconnects in manufacturing MRAM cells
A method of forming dual interconnects in a magnetoresistive memory cell includes: providing an intermediate product including: a metallization layer including...
Switch mode power supply with reduced switching losses
The invention relates to a switching transistor presenting reduced switching losses. In the switching transistor, output capacitance is very high when...
Method and apparatus for checking output signals of an integrated circuit
Apparatus and method for checking output signals of an integrated circuit are provided. One embodiment provides a method for checking whether signals are output...
CMOS-process compatible high-DC surface coating for capacitive detection
and stimulation of biological tissues
Biochip for capacitive stimulation and/or detection of biological tissues. The biochip has a carrier structure, at least one stimulation and/or sensor device,...
RF front-end receiver
An RF front-end receiver comprises a low noise amplifier and a local oscillator driver, which are connected to respective input ports of a mixer which comprises...
Method for wireless data interchange between circuit units within a
package, and circuit arrangement for...
Method for wireless data interchange between circuit units within a package, and circuit arrangement for performing the method. The invention provides a circuit...
Methods of DDR receiver read re-synchronization
A method for reading data is provided. The method includes generating two or more pulses from a first clock signal by which the data to be read is received,...
Voltage supply circuit, in particular for a DRAM memory circuit, as well
as a method for controlling a supply...
A voltage supply circuit for providing an internal supply voltage in an integrated circuit is provided. The voltage supply circuit comprises a supply source for...
Device and procedure for measuring memory cell currents
The invention relates to a procedure and a device for measuring memory cell currents, in particular for non-volatile memory components, where the device has a...
Apparatus and method for spectrally shaping a reference clock signal
Clock signal jitter detection circuit for detecting a clock signal jitter in a reference clock signal (CLK), having a switched-capacitor reference ...
Correction of static mismatch errors in a D/A converter
Methods, articles of manufacture and systems for the correction of static mismatch errors in D/A converters, where an input word, being the digital ...
Differential driver circuit
A current-saving differential wideband driver circuit comprises a differential input amplifier for amplifying a differential input signal to produce a...
Device for setting a clock delay
A device for setting a clock delay is proposed, wherein delayed output clock signals are generated with the aid of delaying means by delaying an input clock...
Drive circuit for a fluorescent lamp with a diagnosis circuit, and method
for diagnosis of a fluorescent lamp
A drive circuit for at least one fluorescent lamp has a half-bridge circuit for production of a supply voltage a resonant tuned circuit coupled to the...
Semiconductor component and corresponding fabrication/mounting method
A semiconductor component (1) has a substrate (21) and a structure (22, 23) formed from semiconductor/insulator/conductor layers (24 to 26) on/in the substrate...
Self-aligned V0-contact for cell size reduction
An FeRAM comprising includes a ferroelectric material sandwiched between a top electrode and a bottom electrode. A V0-contact provides an electrical connection...
Method for patterning a semiconductor component
In a method for patterning a semiconductor component a first cover layer is applied to a first region and a second region of a semiconductor component being...
Method for production of a standard cell arrangement, and apparatus for
carrying out the method
A standard cell arrangement can be produced by automatically determining a distance between at least two standard cells in at least one standard cell row. The...
The present invention relates to a memory arrangement having a controller and having at least one memory device. Data signals, control signals and address...
Method and apparatus for reducing the crest factor of a signal
A method and apparatus for reducing the crest factor of a signal uses a plurality of partial correction signals having respective predetermined frequencies. For...
Method for determining an optimal absorber stack geometry of a
lithographic reflection mask
The present invention relates to a method for determining an optimal absorber stack geometry of a lithographic reflection mask comprising a reflection layer and...
Interleaving circuit for a multiband OFDM transceiver
Interleaving circuit for a multiband OFDM (orthogonal frequency division multiplexing) transceiver of a ultra wide band wireless personal access network...
Integrated semiconductor memory having sense amplifiers selectively
activated at different timing
An integrated semiconductor memory includes a memory cell array in which first sense amplifiers are arranged on a right-hand side of the memory cell array and...
Non-volatile memory device with single transistor memory cell
A non-volatile memory device includes a plurality of word lines, a plurality of sense lines, and a plurality of non-volatile memory cells. Each memory cell...
Low equalized sense-amp for twin cell DRAMs
Embodiments of the invention provide a method and apparatus for accessing a twin cell memory device. In one embodiment, a twin memory cell is accessed using a...
Circuit board for reducing crosstalk of signals
A circuit board includes a first group of layers located close to a top side of the circuit board, and a second group of layers located close to an underside of...
Memory module with an electronic printed circuit board and a plurality of
semiconductor chips of the same type
In a first embodiment, the invention provides a memory module having an electronic printed circuit board and a plurality of semiconductor chips of the same type...
Log circuit and highly linear differential-amplifier circuit
A log circuit receives an operated current signal and a reference current signal at respective inputs and comprises an operand log circuit including a first...
Device and a process for the calibration of a semiconductor component test
A device and a process for the calibration of a semi-conductor component test systemThe invention relates to a process and a device for the calibration of a...
Semiconductor chip with flexible contacts at a face
The present invention relates to a semiconductor chip comprising a semiconductor element, at least a conducting line and a contact area being arranged on the...
Vertical field-effect transistor in source-down structure
The invention relates to a vertical field-effect transistor in source-down structure, in which the active zones (10, 7, 11) are introduced from trenches (5, 8,...
Method for producing semiconductor memory devices and integrated memory
The invention provides an integration scheme for a memory cell array, especially a charge-trapping memory cell array, comprising an architecture of local...
Method for fabricating contact holes in a semiconductor body and a
A method for fabricating contact holes in a semiconductor body proceeds from a structure in which: a plurality of trenches isolated from one another by mesa...
Methods of patterning a magnetic stack of a magnetic memory cell and
Methods of patterning a magnetic stack of a magnetic memory cell and structures thereof. At least the top magnetic material layer of a magnetic stack is...
ECC flag for testing on-chip error correction circuit
The present invention includes an error correction circuit with a data memory, a control circuit, a parity memory, and a recorder. The data memory is configured...
Memory circuit comprising redundant memory areas
The invention relates to a memory circuit comprising regular memory areas and redundant memory areas, redundancy circuits in each case being assigned to the...
Method and apparatus for allocating bus access rights in multimaster bus
A method for allocating bus access rights is used in a multimaster bus system wherein addresses are explicitly allocated to master devices and each master device...
Method for equalization of a payload signal, taking into account an
In a method for equalization of a signal which is transmitted via a payload channel taking into account at least one interference channel, the trellis diagram...
Transmission device with adaptive digital predistortion, transceiver with
transmission device, and method for...
The invention provides a transmission device having adaptive digital predistortion, which has a transmission path and a feedback path. The transmission path...
Integrated memory circuit and method for repairing a single bit error
The invention relates to an integrated memory circuit having a memory cell array comprising memory cells arranged on word lines and bit lines, and having a...
Methods for repairing and for operating a memory component
In a method for repairing a memory component, data retention times of regular memory cells are determined. Weak regular memory cells having a data retention time...
Integrated circuit having resistive memory
A memory device including a memory cell, a first circuit, and a second circuit. The memory cell includes phase-change material. The first circuit is configured...
Memory having CBRAM memory cells and method
A memory cell arrangement has a plurality of memory cells of the CBRAM type and a programming apparatus, the memory cells being arranged along bit lines and each...
Apparatus and method for monitoring trench profiles and for
An apparatus for monitoring a trench profile of a substrate includes a radiation-emitting unit for irradiating the substrate with infrared radiation. The...
Method for calibrating a digital/analog converter and digital/analog
A digital/analog converter comprises a converter array comprised of a plurality of converter cells and a device for self-calibration of the converter cells. The...
The invention is directed to an oscillator circuit in which a frequency-determining resonant circuit includes an inductive element, a first capacitive element...