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Patent # Description
US-7,420,199 Resistivity changing memory cell having nanowire electrode
A memory cell includes a first electrode comprising a nanowire, a second electrode, and phase-change material between the first electrode and the second electrode.
US-7,419,883 Method for fabricating a semiconductor structure having selective dopant regions
A method for fabricating a semiconductor structure having selective dopant regions in a semiconductor substrate having trenches formed therein I disclosed. In...
US-7,419,549 Nozzle assembly for applying a liquid to a substrate
The aim of the invention is to achieve a rapid, homogeneous application of a liquid with as little force as possible to a substrate. To achieve this, the...
US-7,418,631 Program-controlled unit
A program-controlled unit has debug resources for monitoring the operations proceeding within the program-controlled unit. The program-controlled unit described...
US-7,418,055 Device and method for regulating the output power of mobile
In mobile radio receivers, the transmission power must be raised before the start of the transmission process, and must be reduced again after the end of the...
US-7,417,839 Zener-zap memory
In an integrated circuit for electrically permanently program information in the integrated circuit a current is driven through an NPN-transistor. The integrated...
US-7,417,736 Method for determining a radiation power and an exposure apparatus
Method for determining a mean radiation power ##EQU00001## of electromagnetic radiation of a radiation source, the radiation being intensity-modulated with...
US-7,417,576 Method and apparatus for detecting an edge
A detector comprises an analog-to-digital converter. The analog-to-digital converter comprises an input for an analog receive signal and an output for a digital...
US-7,417,506 Amplifier having switchable negative feedback
An amplifier having programmable amplification includes a transistor circuit having a plurality of negative feedback resistors, a switch being associated to a...
US-7,417,301 Semiconductor component with coreless transformer
The invention relates to a semiconductor component having a coreless first transformer (71, 72) which comprises a first (71) and a second (72) planar winding, is...
US-7,417,248 Transistor with shallow germanium implantation region in channel
A method of manufacturing a transistor and a structure thereof, wherein a very shallow region having a high dopant concentration of germanium is implanted into a...
US-7,417,247 Pentaarylcyclopentadienyl units as active units in resistive memory elements
Polymers are described which exhibit a resistive hysteresis effect. The polymers include a polymer backbone to which pentaarylcyclopentadienyl radicals are...
US-7,417,245 Phase change memory having multilayer thermal insulation
A memory cell includes a first electrode, a second electrode, phase-change material contacting the first electrode and the second electrode, multilayer thermal...
US-7,417,240 Apparatus for producing secondary electrons, a secondary electrode, and an acceleration electrode
An apparatus includes a primary electrode and an acceleration electrode. The acceleration electrode or, alternatively, an additional secondary electrode contains...
US-7,417,198 Radiofrequency power semiconductor module with cavity housing, and method for producing it
The invention relates to a radiofrequency power semiconductor module having a cavity housing constructed from three modules, a 1st module, which has an upwardly...
US-7,416,976 Method of forming contacts using auxiliary structures
A semiconductor product includes a substrate having a substrate surface. A plurality of wordlines are arranged at a distance from one another and running along a...
US-7,416,952 Method for producing a dielectric interlayer and storage capacitor with such a dielectric interlayer
A dielectric interlayer, especially for a storage capacitor, is formed from a layer sequence subjected to a temperature process, wherein the layer sequence has...
US-7,416,927 Method for producing an SOI field effect transistor
Method for producing a first SOI field effect transistor with predetermined transistor properties by forming a laterally delimited layer sequence with a...
US-7,415,885 Concept for testing a pressure sensor and a nozzle
A device for testing a pressure sensor having a pressure-sensitive region includes a fixture for a pressure sensor designed to receive the pressure sensor, a...
US-7,415,649 Semi-conductor component test device with shift register, and semi-conductor component test procedure
The invention relates to a semi-conductor component test procedure, as well as to a semi-conductor component test device with a shift register, which comprises...
US-7,415,602 Apparatus and method for processing a sequence of jump instructions
An apparatus for processing a sequence of instructions, which comprises a LCALL instruction, a FCALL instruction and a common re-jump instruction (return),...
US-7,415,581 Semiconductor memory chip
A semiconductor memory chip in which signals are transferred as serial signal frames includes a frame decoder providing an interface between a memory core and a...
US-7,415,569 Memory including a write training block
A memory includes a plurality of first-in-first-out (FIFO) cells, an output pointer counter and a write training block. The output pointer counter is for...
US-7,415,077 Transmission arrangement, particularly for mobile radio
The invention specifies a transmission arrangement, particularly for mobile radio, which has a homodyne design and in which a feedback path is routed from the...
US-7,414,917 Re-driving CAwD and rD signal lines
Semiconductor memory modules and semiconductor memory systems using the same are described herein. The modules divide a conventional DIMM into a series of...
US-7,414,906 Memory component having a novel arrangement of the bit lines
A memory component comprises a plurality of bit lines, on which memory cells are arranged, and a plurality of sense amplifiers, which are arranged in a row, each...
US-7,414,899 Method and apparatus for early write termination in a semiconductor memory
A synchronous DRAM (SDRAM) terminates a write operation in response to detecting deactivation of a data strobe signal applied to it during the write operation....
US-7,414,896 Technique to suppress bitline leakage current
Methods and apparatus that may help reduce standby current in memory devices are provided. By separating equalizing and precharging functions into separate...
US-7,414,496 Filter structure and method for the design of a filter
A filter structure comprises a filter having an input port and an output port and a carrier to which the filter is attached having a reference potential area....
US-7,414,465 Amplifier arrangement
An amplifier arrangement has a first transistor and at least one further transistor. The amplifier arrangement furthermore includes a first coupling impedance,...
US-7,414,421 Insertable calibration device
An insertable calibration device for a programmable tester apparatus comprises at least one calibration unit and a control unit. The progammable tester apparatus...
US-7,414,311 Ball grid array housing having a cooling foil
A ball grid array housing, a semiconductor device having a ball grid array housing and an electronic circuit are disclosed. In one embodiment, a ball grid array...
US-7,414,286 Trench transistor and method for fabricating a trench transistor
A trench transistor having a semiconductor body, in which a trench structure and an electrode structure embedded in the trench structure is disclosed. The...
US-7,414,257 Switching device for configurable interconnect and method for preparing the same
The present invention relates to a switching device to be irreversibly switched from an electrically isolating off-state into an electrically conducting on-state...
US-7,413,993 Process for removing a residue from a metal structure on a semiconductor substrate
The invention is concerned with a process for removing residue comprising a polymeric resist and metal oxide from a metal structure on a semiconductor substrate,...
US-7,413,833 Single exposure of mask levels having a lines and spaces array using alternating phase-shift mask
An active area pattern is formed atop a deep trench pattern with a single exposure using an alternative phase-shift mask. To prevent adjacent spaces of opposite...
US-7,413,353 Device and method for data transmission between structural units connected by an articulated joint
A device for transmitting data between two structural units connected to one another by an articulated joint has a long service life which permits a high...
US-7,412,608 Secure data processing unit, and an associated method
A secure data processing unit has a data/program instruction memory for storing data/program instructions, an instruction line with a large number of function...
US-7,412,593 Processor for processing a program with commands including a mother program and a sub-program
A processor for processing a program with commands, which has a mother program with a sub-program jump command and a sub-program, which is to be processed in...
US-7,412,217 Transceiver with interference signal rejection, and method for interference signal rejection
A transceiver with interference signal rejection has a transmission path and a reception path. The transmission path is connected to a transmission amplifier...
US-7,412,010 Frequency correction in a mobile radio receiver using an analogue and a digital control loop
A mobile communication system is provided with a system for frequency correction in a reception apparatus which has a first control system, device or loop for...
US-7,411,920 Method for transmitting frames in a wireless local area network
On the case of receiving data frame from a station, the method of the present invention instructs the repeater to replace the content of the receiver address...
US-7,411,898 Preamble generator for a multiband OFDM transceiver
Preamble generator for a multiband frequency division multplexing (OFDM) tranceiver of a wireless personal area network (WPAN) being switchable between a time...
US-7,411,854 System and method for controlling constant power dissipation
A method for controlling the constant power dissipation of a memory cell includes initially measuring the resistance of the memory cell, and subsequently...
US-7,411,844 Semiconductor memory device having a redundancy information memory directly connected to a redundancy control...
A semiconductor memory device (M) includes a memory array (MA) having a plurality of memory cells, a redundancy array (RA) having a plurality of memory cells, a...
US-7,411,843 Semiconductor memory arrangement with branched control and address bus
A semiconductor memory arrangement for operation in a data memory system with at least one semiconductor memory chip for the storage of user data includes a...
US-7,411,837 Method for operating an electrical writable and erasable memory cell and a memory device for electrical memories
A method is provided for operating an electrical writable and erasable memory cell, which has a channel region that can be operated in a first and a second...
US-7,411,835 Discharge circuit for a capacitive load
A circuit arrangement for the defined discharge of a capacitive load includes a first connecting terminal for connection of the load, a second connecting...
US-7,411,822 Nonvolatile memory cell arrangement
Memory transistors are arranged in a plurality of rows and columns. A first source/drain terminal of each memory transistor of a first column is connected to an...
US-7,411,815 Memory write circuit
A design for a memory array that uses bi-directional write currents and that avoids switched ground connections for memory cells, thereby reducing signal loss...
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