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Memory array architecture and method for high-speed distribution
A method includes an initial process of selecting a memory cell within the memory array and an operating condition under which the memory cell is to be tested....
Differential read-out circuit for fuse memory cells
A read-out circuit is disclosed, where the circuit reads information out of a memory unit comprising two non-volatile memory cells. The cells have different...
Non-volatile semiconductor memory device and method for operating a
non-volatile memory device
Embodiments of the invention relate to non-volatile memory devices and their methods of manufacture. Embodiments comprise an array of non-volatile memory cells,...
Frequency modulator and frequency modulation method
A frequency modulation method is provided in which the frequency of a carrier signal is modulated on the basis of the frequency of a modulation signal, and in...
Duty cycle detector with first and second oscillating signals
A duty cycle detector including a first circuit, a second circuit, and a third circuit. The first circuit is configured to receive a clock signal having a first...
Electronic switching circuit, switching circuit test arrangement and
method for determining the operativeness...
The invention relates to an electronic switching circuit in which a plurality of test circuit blocks is provided, whereby every test circuit block comprises a...
Multi-chip device and method for producing a multi-chip device
The present invention relates to a multi-chip device comprising a substrate having a first surface on which a number of first contact elements is provided, a...
Method for fabricating a capacitor
The present invention relates to a method of fabricating a capacitor in a semiconductor substrate. The capacitor is fabricated such that the capacitor comprises:...
Field effect semiconductor switch and method for fabricating it
A field effect semiconductor comprises a semiconductor layer having a surface, a first and a second semiconductor region in the semiconductor layer, which are...
Charge-trapping memory device and methods for operating and manufacturing
To manufacture a memory device, a gate dielectric layer is formed over a semiconductor body and a gate electrode layer is formed over the gate dielectric layer....
Process for fabricating a semiconductor device having deep trench
A process for fabricating a semiconductor device having deep trench structures includes forming a first portion of the trench in a semiconductor substrate and a...
Arrangement for transferring information/structures to wafers
An arrangement for transferring information/structures to wafers uses a stamp on which the information/structures to be transferred have been applied as elevated...
Repair of semiconductor memory device via external command
A semiconductor integrated circuit memory device is repaired by receiving an externally-supplied signal containing failure information that identifies at least...
Integrated circuit including a memory having low initial latency
A random access memory comprises an array of memory cells and a controller. The controller is configured to access the array of memory cells in a double data...
Device and method for testing integrated circuits
A test device and method is disclosed. In one embodiment, the test device includes a precision signal generator for generating a test signal, which generator is...
Integrated voice-over-internet protocol processor
A single-chip network processor (12) for a Voice-over-Internet Protocol phone integrates a universal serial bus port (21), a pair of IEEE 802.3 MACs (40), and...
Memory element, memory read-out element and memory cell
A memory element comprises a resistance element having a first resistance value in a first state and a second resistance value in a second state, it being...
Apparatus for measuring an exposure intensity on a wafer
An apparatus for measuring an exposure intensity on a wafer is disclosed. According to one aspect, an apparatus for measuring an exposure intensity on a wafer...
Methods of forming silicide
Methods of fully siliciding semiconductive materials of semiconductor devices are disclosed. A preferred embodiment comprises depositing an alloy comprised of a...
Methods of fabricating semiconductor devices and structures thereof
Methods of forming spacers on sidewalls of features of semiconductor devices and structures thereof are disclosed. A preferred embodiment comprises a...
Method of forming a charge-trapping memory device
In a charge-trapping device having an array of memory cells, which are controlled by word lines buried in trenches within a substrate, further trenches are...
Loop-back method for measuring the interface timing of semiconductor
devices with the aid of signatures and/or...
The invention relates to a method for testing a memory device with the memory device being able to be operated in a normal operating mode and a test mode and...
Integrated transceiver circuit with low interference production and
An integrated transceiver circuit has a reception path, which in turn has a mixer unit for demodulation of a received signal. An analog/digital converter unit is...
Write burst stop function in low power DDR sDRAM
A write burst stop command function is provided for a semiconductor memory device, and in particular for a memory device having a write latency, such as is...
Technique to suppress leakage current
Embodiments of the invention generally provide a method and wordline driver having a reduced leakage current. In one embodiment, a wordline is driven to a...
Semiconductor memory array with serial control/address bus
A semiconductor memory array for operation in a data storage system with at least one semiconductor memory chip for the storage of user data and one memory...
Method for driving a switch that controls current drawn in a power factor
correction circuit and a drive...
The invention relates to a method for provision of a drive signal for a switch which controls the current drawn by an inductive energy storage element in a power...
Amplifier arrangement having an adjustable gain, and use thereof
According to one or more aspects of the present invention, an amplifier arrangement is disclosed. The arrangement comprises a first, a second and a third...
A chip module having a chip which is mounted by means of chip adhesive on a mount and is electrically connected via bonding wires to contact pads, and an...
Semiconductor wafer, an electronic component, and a component carrier for
producing the electronic component
An electronic component includes a semiconductor chip with a chip topside, an integrated circuit, and a chip backside. The chip backside includes a magnetic...
A monolithically integrated bipolar transistor has an SOI substrate, a collector region in the SOI substrate, a base layer region on top of and in contact with...
Method for contacting parts of a component integrated into a semiconductor
The invention relates to a method for contacting parts of a component integrated into a semiconductor substrate (1). According to the inventive method, a first...
Fabrication of organic electronic circuits by contact printing techniques
A method for fabricating an organic conductor path on a substrate includes providing a printing stamp with a hydrophobic patterned printing side that is loaded...
Post exposure resist bake
A preferred embodiment of the invention provides a method for forming an integrated circuit. The method comprises forming a resist layer on a substrate....
Carrier tape for electronic components
A carrier tape for electrical components is provided comprising a tape having a length and a plurality of cavities along the length of the tape. Each cavity...
Electronic circuit with energy control
An inventive electronic circuit includes a controller for processing a processor task as well as an energy determination means for determining the energy...
Fuse memory cell with improved protection against unauthorized access
A memory device is provided, the memory device having a memory cell, a programming unit for programming the memory cell, and a switching unit for optionally...
Bit line dummy core-cell and method for producing a bit line dummy
A bit line dummy core-cell comprises at least a first inverter and at least a second inverter which are cross coupled to form a bistable flip-flop. The first...
Switching mode power supplies
In a switching mode power supply, an input received from the secondary side of the transformer 7 and indicative of the power being drawn by the loads is used to...
Phase-locked loop and method for operating a phase-locked-loop
A phase-locked loop suitable for mobile radio communications and a method for operating the same is disclosed. One embodiment of the phase-locked loop comprises...
Semiconductor memory device with channel regions along sidewalls of fins
A semiconductor memory (26) having a plurality of memory cells (25), the semiconductor memory (26) having a substrate (1), at least one wordline (2) and first...
Process for producing layer structures for signal distribution
Structures for signal distribution are produced by applying a metallic seed layer over a semiconductor body. An insulating layer is applied over the metallic...
Method for fabricating a trench isolation structure having a high aspect
A method for fabricating a trench isolation structure wherein a trench is formed in a silicon body and an oxide layer is formed in the trench. The silicon body...
Post-silicide spacer removal
A method forms a gate conductor over a substrate, forms spacers (e.g., nitride spacers) on sides of the gate conductor, and implants an impurity into exposed...
Semiconductor chip with metallization levels, and a method for formation
in interconnect structures
A metallization surface (5), which acts as an etching stop layer during the production of openings (4) in a passivation layer (3) applied to its upper face and...
Set of masks including a first mask and a second trimming mask with a
semitransparent region having a...
A set of at least two masks for the projection of structure patterns coordinated with one another by a projection system into the same photosensitive layer of a...
Set of at least two masks for the projection of structure patterns
A set of at least two masks, coordinated with one another, for the projection of structure patterns, into the same photosensitive layer arranged on a...
Socket and/or adapter device, and an apparatus and process for loading a
socket and/or adapter device with a...
The invention refers to a process for loading a socket and/or adapter device with a corresponding semi-conductor component, a socket and/or adapter device, a...
Method and apparatus for testing DRAM memory chips in multichip memory
Method and apparatus for testing memory cells of a DRAM memory chip arranged together with a nonvolatile memory chip in a multichip memory module. The multichip...
Semiconductor memory chip
A semiconductor memory chip includes: a reception interface section for receiving external data, command, and address signals in form of serial signal frames; an...