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Patent # Description
US-7,443,713 Integrated semiconductor memory and method for operating a semiconductor memory
An integrated semiconductor memory device includes at least one memory cell, at least one sense amplifier and a pair of bit lines connected to each sense...
US-7,443,484 Method for exposing a semiconductor wafer by applying periodic movement to a component
A method of focus variation is described herein to achieve a one-step exposure of a wafer without the limitation of applying a complex y-tilt to a wafer stage....
US-7,443,254 Relaxation oscillator with propagation delay compensation for improving the linearity and maximum frequency
A tunable oscillator comprises a control supply configured to output a control output operable to tune the tunable oscillator. The tunable oscillator further...
US-7,443,247 Circuit arrangement for detection of a locking condition for a phase locked loop, and a method
A circuit arrangement includes a phase locked loop, having a phase detector on whose output side a phase signal can be tapped off and whose output side is...
US-7,443,238 Amplifier stage, operational amplifier and method for amplifying a signal
An amplifier stage includes a first and a second signal path having a series connection of a first transistor of a first conduction type which forms a control...
US-7,443,199 Circuit arrangement for voltage selection, and method for operating a circuit arrangement for voltage selection
The circuit arrangement includes a first and a second input to supply a first and a second supply voltage and also an output. The circuit arrangement includes a...
US-7,443,178 Circuit arrangement of the temperature compensation of a measuring resistor structure
An electrical circuit for the temperature compensation of at least one measuring resistor structure integrated in a semiconductor body includes at least one...
US-7,443,019 Semiconductor device with conductor tracks between semiconductor chip and circuit carrier and method for...
The invention relates to a semiconductor device with conductor tracks between a semiconductor chip and a circuit carrier, and to a method for producing the same....
US-7,443,014 Electronic module and method of assembling the same
An electronic module includes a semiconductor power switch and a semiconductor diode. The lower side of the semiconductor power switch includes an output contact...
US-7,442,756 Polymer for sealing porous materials during chip production
A compound and method for sealing or protecting porous materials used in semiconductor fabrication, and in particular for protecting the inner walls of trenches...
US-7,442,624 Deep alignment marks on edge chips for subsequent alignment of opaque layers
A method of forming alignment marks on edge chips in a kerf region of a semiconductor workpiece. The alignment marks are formed in at least one material layer of...
US-7,442,609 Method of manufacturing a transistor and a method of forming a memory device with isolation trenches
A method of manufacturing a transistor. In one embodiment, the method includes forming a gate electrode by defining a gate groove in the substrate. A plate-like...
US-7,442,605 Resistively switching memory
The present invention relates to a reproducible conditioning during the manufacturing of a resistively switching CBRAM memory cell comprising a first electrode...
US-7,442,582 Method for producing a chip-substrate connection
A method and an apparatus for producing a chip-substrate connection by alloying or brazing, using a solder containing two or more components with at least two...
US-7,440,861 Concept of compensating for piezo influences on integrated circuitry
The inventive circuitry on a semiconductor chip includes a first functional element having a first electronic functional-element parameter that exhibits a...
US-7,440,499 Fractional spaced equalizer
Fractional Spaced Equalizer FSEQ having adjustable coefficients ci for equalizing a reception signal of a transceiver. The transceiver comprises an echo...
US-7,440,402 Hybrid DSL system for transmission of hybrid DSL data via a subscriber access line in order to increase the...
The hybrid DSL system (10) for transmission of hybrid DSL data via a subscriber access line (2030) has a baseband transceiver (101) for transmission of first...
US-7,440,334 Multi-transistor memory cells
A memory cell having three transistors and a capacitor having metallic electrodes is described. Multiple memory cells may be arranged in a memory unit or array....
US-7,440,309 Memory having parity error correction
A memory includes a sense amplifier segment and a plurality of word lines including a spare word line, a first transfer word line, and a second transfer word...
US-7,439,824 Bulk acoustic wave filter and method for eliminating unwanted side passbands
A bulk acoustic wave (BAW) filter (40) is fabricated from thin film bulk acoustic wave resonators and a method eliminates unwanted side passbands. This BAW...
US-7,439,765 Mask-programmable logic macro and method for programming a logic macro
A mask-programmable logic macro includes at least three input terminals an output terminal and a first set of transistors comprised of at least three transistors...
US-7,439,761 Apparatus and method for controlling a driver strength
Method of controlling a driver strength and a termination impedance of a signal line of an interface, wherein the driver sends an output signal as an alternating...
US-7,439,591 Gate layer diode method and apparatus
Method, apparatus, and article of manufacture for a diode defined by a portion of a gate layer of an integrated circuit. Illustrative, non-limiting embodiments...
US-7,439,579 Power semiconductor with functional element guide structure
A trench transistor is described. In one aspect, the trench transistor has a cell array having a plurality of cell array trenches and a plurality of mesa zones...
US-7,439,198 Method for fabricating a buried metallic layer in a semiconductor body and semiconductor component having a...
A method for fabricating a buried metallic layer at a predetermined vertical position in a semiconductor body having a first and second side includes a step of...
US-7,439,186 Method for structuring a silicon layer
A method for structuring a silicon layer applies lacquer mask onto the silicon layer, and the silicon layer is selectively etched relative to the lacquer mask...
US-7,439,125 Contact structure for a stack DRAM storage capacitor
A method for fabricating a contact structure for a stack storage capacitor includes forming the contact structure in a node contact region with contact openings,...
US-7,437,696 Method and device for determining the time response of a digital circuit
A method and a device determine a time response of a digital circuit. The time response is determined as a time difference between a data delay of a data path of...
US-7,437,692 Memory debugger for system-on-a-chip designs
A simulation/debugging method for SOC designs that utilizes initial memory values loaded into a simulation model. A test program is then executed, and incremetal...
US-7,437,629 Method for checking the refresh function of an information memory
A method for checking the refresh function of a memory having a refresh device includes the steps of, first, ascertaining whether or not refresh request pulses...
US-7,437,627 Method and test device for determining a repair solution for a memory module
Method for determining a repair solution for a memory module in a test system, memory areas of the memory module being successively tested in order to obtain,...
US-7,437,572 Key management device and method for the encrypted storage of digital data words
Key management device for electronic memories and a method for the encrypted storage of digital data words in electronic memories, in which each stored data word...
US-7,437,260 Concept of compensating for piezo influences on integrated circuitry
A semiconductor chip includes a first functional element having a first electronic functional-element parameter exhibiting a dependence relating to the...
US-7,436,721 Supplying voltage to a bit line of a memory device
A method supplies voltage to a bit line of a memory device. The method includes precharging, with a precharging device, the bit line to an output potential,...
US-7,436,700 MRAM memory cell having a weak intrinsic anisotropic storage layer and method of producing the same
An MRAM memory cell is provided having a layer system made of circular-disk-shaped layers. The memory cell includes first and second magnetic layers separated by...
US-7,436,695 Resistive memory including bipolar transistor access devices
A memory includes a first bipolar transistor, a first bit line, and a first resistive memory element coupled between a collector of the first bipolar transistor...
US-7,436,694 Nonvolatile memory cell
Nonvolatile memory cell, having a first resistor that is electrically programmable in a nonvolatile fashion, a second resistor that is electrically programmable...
US-7,436,314 Monitor and circuit arrangement for voltage regulator
A circuit arrangement having a voltage regulator, which is designed to generate a regulated operating voltage, and a voltage monitoring unit, which is designed...
US-7,436,290 Sensor discrimination apparatus, system, and method
A first and second node configured to couple to a load. A current source is adapted to drive a first current to the load through at least one of the first and...
US-7,436,249 Circuit and method for filtering a radio frequency signal
A circuit for filtering a radio frequency signal at a given frequency comprises an input terminal, a filter device, and an active AC shunt circuit having first...
US-7,436,236 Analog DC compensation
Arrangement for analog compensation of a DC component in an AC signal having an estimator for producing an estimate corresponding to the DC component, a...
US-7,436,195 Test apparatus for semiconductor elements on a semiconductor wafer, and a test method using the test apparatus
A test apparatus for semiconductor elements on a semiconductor wafer has test probes in a test area, which are held by a needle card. The needle card is held by...
US-7,436,072 Protected chip stack
A protected chip stack having a first chip and a second chip on the first chip. A functional layer in at least the first chip or the second chip. On the first...
US-7,436,023 High blocking semiconductor component comprising a drift section
A semiconductor component having a drift path (2) which is formed in a semiconductor body (1), is composed of a semiconductor material of first conductance type....
US-7,436,016 MIM capacitor with a cap layer over the conductive plates
A method for forming a MIM capacitor and a MIM capacitor device formed by same. A preferred embodiment comprises selectively forming a first cap layer over a...
US-7,434,740 Method and apparatus for position detection
The invention relates to a method and an apparatus (4) for detecting the position of a sequence of markings (2) on a carrier (1) in relation to a detector (3)...
US-7,434,222 Task context switching RTOS
A task switch from a first data processing task to a second data processing task can be accomplished by the first task calling a function which saves the first...
US-7,434,143 Method and arrangement for detecting a collision in a communication network
A method and an arrangement for detecting a collision in a communication network, such as a WLAN, on which data are sent in frames of variable lengths separated...
US-7,434,125 Integrated circuit, test system and method for reading out an error datum from the integrated circuit
An integrated circuit is provided, the integrated circuit having a test circuit for reading out an error datum from the integrated circuit in accordance with a...
US-7,434,121 Integrated memory device and method for its testing and manufacture
An integrated memory device includes an array of memory cells for storing data, a memory cell selector operationally connected to the array for selecting at...
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